Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY27410 4-PLL Spread-Spectrum Clock Generator 4-PLL Spread-Spectrum Clock Generator Up to 100-ps skew for differential outputs within a bank Features Four fractional N-type phase-locked loops (PLLs) with Input frequencies VCXO (120 ppm with steps of 0.23 ppm) Crystal input: 8 MHz to 48 MHz Spread-spectrum capability (Logic SS and Lexmark profile Reference clock: 8 MHz to 250 MHz LVCMOS 0.1% to 5% in 0.1% steps, down or center spread) Reference clock: 8 MHz to 700 MHz differential Supply voltage: 1.8 V, 2.5 V, and 3.3 V Output frequencies Zero-delay buffer (ZDB) and non-zero delay buffer (NZDB) 25 MHz to 700 MHz LVDS, LVPECL, HCSL, CML configurations 3 MHz to 250 MHz LVCMOS 2 1kHz to 8MHz for one LVCMOS output I C configurable with onboard programming RMS phase jitter: 1-ps max at 12-kHz to 20-MHz offset Industrial-grade device, offered in 48-pin QFN (7 7 1.0 mm) package PCIe 1.0/2.0/3.0 compliant SATA 2.0, USB 2.0/3.0, 1/10-GbE compliant Functional Description Maximum 12 outputs split in two banks with six outputs each. The CY27410 device configuration can be created using Up to eight differential output pairs (HCSL, LVPECL, CML, ClockWizard 2.1. For programming support, contact Cypress or LVDS) technical support or send an email to clocks cypress.com. Up to 12 LVCMOS outputs For a complete list of related documentation, click here. Logic Block Diagram Output Drivers 1 VIN ADC FS2 FS1 O1 1..4 O2 1..4 FS FS0 SCLK I2C PLL1 PLL2 SDAT XIN RCAL XOUT INI IN1P IN1S RCCAL Reference IN1N System IN2S Register INC IN2P Memory BG IN2N OSC PLL3 PLL4 NV Memory POR O3 1..4 O4 1..4 QP PRG VDD Block LDOs Output Drivers 2 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-89074 Rev. *M Revised February 15, 2019 OUT21P OUT11P OUT21N OUT11N OUT22P OUTC OUTC OUT12P OUT22N OUT12N OUT23P OUT13P O3 1..4 O1 1..4 OUT23N OUT13N INC OUT24P INC OUT14P IN1S OUT24N IN1S OUT14N IN2S IN2S VDDIO D2 VDDIO D1 VDDIO S2 VDDIO S1 OUT25 O4 1..4 O2 1..4 OUT15 OUT26 INC INC OUT16 IN1S IN1S IN2S IN2S