CY62126EV30 MoBL 1-Mbit (64 K 16) Static RAM 1-Mbit (64 K 16) Static RAM Features Functional Description High speed: 45 ns The CY62126EV30 is a high performance CMOS static RAM organized as 64K words by 16 bits. This device features Temperature ranges advanced circuit design to provide ultra low active current. This Industrial: 40 C to +85 C is ideal for providing More Battery Life (MoBL ) in portable Automotive: 40 C to +125 C applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power Wide voltage range: 2.2 V to 3.6 V consumption when addresses are not toggling. Placing the Pin compatible with CY62126DV30 device in standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The input and Ultra low standby power output pins (I/O through I/O ) are placed in a high impedance 0 15 Typical standby current: 1 A state when the device is deselected (CE HIGH), the outputs are Maximum standby current: 4 A disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write Ultra low active power operation (CE LOW and WE LOW). Typical active current: 1.3 mA at f = 1 MHz To write to the device, take Chip Enable (CE) and Write Enable Easy memory expansion with CE and OE features (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O through I/O ) is written into the location 0 7 Automatic power down when deselected specified on the address pins (A through A ). If Byte High 0 15 Complementary metal oxide semiconductor (CMOS) for Enable (BHE) is LOW, then data from I/O pins (I/O through 8 optimum speed and power I/O ) is written into the location specified on the address pins 15 (A through A ). 0 15 Offered in Pb-free 48-ball very fine-pitch ball grid array To read from the device, take Chip Enable (CE) and Output (VFBGA) and 44-pin thin small outline package (TSOP) II Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If packages Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O to I/O . If 0 7 Byte High Enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 11 for a 8 15 complete description of read and write modes. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 64K x 16 6 A 5 I/O I/O RAM Array 0 7 A 4 A 3 I/O I/O 8 15 A 2 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05486 Rev. *I Revised May 31, 2011 + Feedback ROW DECODER A 11 A 12 A 13 A 14 A 15 SENSE AMPS CY62126EV30 MoBL Contents Pin Configuration .............................................................3 Write Cycle No. 4 Product Portfolio ..............................................................3 (BHE/BLE controlled, OE LOW) .......................................10 Maximum Ratings .............................................................4 Truth Table ......................................................................11 Operating Range ...............................................................4 Ordering Information ......................................................12 Electrical Characteristics .................................................4 Ordering Code Definitions .........................................12 Capacitance ......................................................................5 Package Diagrams ..........................................................13 Thermal Resistance ..........................................................5 Acronyms ........................................................................15 Data Retention Characteristics .......................................6 Document Conventions .................................................15 Switching Characteristics ................................................7 Units of Measure .......................................................15 Switching Waveforms ......................................................8 Document History Page .................................................16 Read Cycle No. 1 (Address transition controlled) .......8 Sales, Solutions, and Legal Information ......................18 Read Cycle No. 2 (OE controlled) ...............................8 Worldwide Sales and Design Support .......................18 Write Cycle No. 1 (WE controlled) ...............................9 Products ....................................................................18 Write Cycle No. 2 (CE controlled) ...............................9 PSoC Solutions .........................................................18 Write Cycle No. 3 (WE controlled, OE LOW .............10 Document Number: 38-05486 Rev. *I Page 2 of 18 + Feedback