CY62126EV30 MoBL 1-Mbit (64 K 16) Static RAM 1-Mbit (64 K 16) Static RAM Features Functional Description High speed: 45 ns The CY62126EV30 is a high performance CMOS static RAM organized as 64K words by 16 bits. This device features Temperature ranges advanced circuit design to provide ultra low active current. This Industrial: 40 C to +85 C is ideal for providing More Battery Life (MoBL ) in portable Automotive-A: 40 C to +85 C applications such as cellular telephones. The device also has an Automotive-E: 40 C to +125 C automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the Wide voltage range: 2.2 V to 3.6 V device in standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The input and Pin compatible with CY62126DV30 output pins (I/O through I/O ) are placed in a high impedance 0 15 Ultra low standby power state when the device is deselected (CE HIGH), the outputs are Typical standby current: 1 A disabled (OE HIGH), both Byte High Enable and Byte Low Maximum standby current: 4 A Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). Ultra low active power To write to the device, take Chip Enable (CE) and Write Enable Typical active current: 1.3 mA at f = 1 MHz (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data Easy memory expansion with CE and OE features from I/O pins (I/O through I/O ) is written into the location 0 7 specified on the address pins (A through A ). If Byte High 0 15 Automatic power down when deselected Enable (BHE) is LOW, then data from I/O pins (I/O through 8 Complementary metal oxide semiconductor (CMOS) for I/O ) is written into the location specified on the address pins 15 optimum speed and power (A through A ). 0 15 To read from the device, take Chip Enable (CE) and Output Offered in Pb-free 48-ball very fine-pitch ball grid array Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If (VFBGA) and 44-pin thin small outline package (TSOP) II Byte Low Enable (BLE) is LOW, then data from the memory packages location specified by the address pins appear on I/O to I/O . If 0 7 Byte High Enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 11 for a 8 15 complete description of read and write modes. For a complete list of related documentation, click here. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 64K x 16 A 6 A 5 RAM Array I/O I/O 0 7 A 4 A 3 I/O I/O 8 15 A 2 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05486 Rev. *P Revised November 24, 2017 ROW DECODER A 11 A 12 A 13 A 14 A 15 SENSE AMPS CY62126EV30 MoBL Contents Pin Configuration .............................................................3 Ordering Information ...................................................... 12 Product Portfolio ..............................................................3 Ordering Code Definitions ......................................... 12 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 13 Operating Range ...............................................................4 Acronyms ........................................................................15 Electrical Characteristics .................................................4 Document Conventions ................................................. 15 Capacitance ......................................................................5 Units of Measure ....................................................... 15 Thermal Resistance ..........................................................5 Document History Page ................................................. 16 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 18 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 18 Data Retention Waveform ................................................6 Products ....................................................................18 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 18 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 18 Truth Table ......................................................................11 Technical Support ..................................................... 18 Document Number: 38-05486 Rev. *P Page 2 of 18