CY62136EV30 MoBL 2-Mbit (128 K 16) Static RAM 2-Mbit (128 K 16) Static RAM Features Functional Description Very high speed: 45 ns The CY62136EV30 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features Wide voltage range: 2.20 V to 3.60 V advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life (MoBL ) in portable Pin compatible with CY62136CV30 applications such as cellular telephones. The device also has an Ultra low standby power automatic power down feature that significantly reduces power Typical standby current: 1 A consumption when addresses are not toggling. The device can also be put into standby mode reducing power consumption by Maximum standby current: 7 A more than 99% when deselected (CE HIGH). The input/output Ultra low active power pins (I/O through I/O ) are placed in a high impedance state 0 15 Typical active current: 2 mA at f = 1 MHz when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, Easy memory expansion with CE and OE features BLE HIGH), or during a write operation (CE LOW and WE LOW). Automatic power down when deselected Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is Complementary metal oxide semiconductor (CMOS) for LOW, then data from I/O pins (I/O through I/O ), is written into optimum speed/power 0 7 the location specified on the address pins (A through A ). If 0 16 Offered in a Pb-free 48-ball very fine ball grid array (VFBGA) Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 8 and 44-pin thin small outline package (TSOP II) packages through I/O ) is written into the location specified on the address 15 pins (A through A ). 0 16 Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O to I/O . If Byte High Enable (BHE) is LOW, then data from 0 7 memory appear on I/O to I/O . See the Truth Table on page 11 8 15 for a complete description of read and write modes. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 A 128K x 16 5 A 4 RAM Array I/O I/O 0 7 A 3 I/O I/O A 8 15 2 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05569 Rev. *F Revised August 22, 2013 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 SENSE AMPS CY62136EV30 MoBL Contents Pin Configuration .............................................................3 Ordering Information ...................................................... 12 Product Portfolio ..............................................................3 Ordering Code Definitions ......................................... 12 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 13 Operating Range ...............................................................4 Acronyms ........................................................................15 Electrical Characteristics .................................................4 Document Conventions ................................................. 15 Capacitance ......................................................................5 Units of Measure ....................................................... 15 Thermal Resistance ..........................................................5 Document History Page ................................................. 16 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 17 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 17 Data Retention Waveform ................................................6 Products ....................................................................17 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 17 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 17 Truth Table ......................................................................11 Technical Support ..................................................... 17 Document Number: 38-05569 Rev. *F Page 2 of 17