CY62137EV30 MoBL 2-Mbit (128 K 16) Static RAM 2-Mbit (128 K 16) Static RAM is ideal for providing More Battery Life (MoBL ) in portable Features applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power Very high speed: 45 ns consumption by 90% when addresses are not toggling. The Wide voltage range: 2.20 V to 3.60 V device can also be put into standby mode reducing power consumption when deselected (CE HIGH or both BLE and BHE Pin compatible with CY62137CV30 are HIGH). The input and output pins (I/O through I/O ) are 0 15 Ultra low standby power placed in a high impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Typical standby current: 1 A Low Enable are disabled (BHE, BLE HIGH), or during a write Maximum standby current: 7 A operation (CE LOW and WE LOW). Ultra low active power Writing to the device is accomplished by asserting Chip Enable Typical active current: 2 mA at f = 1 MHz (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable Easy memory expansion with CE and OE features (BLE) is LOW, then data from I/O pins (I/O through I/O ), is 0 7 written into the location specified on the address pins (A through 0 Automatic power-down when deselected A ). If Byte High Enable (BHE) is LOW, then data from I/O pins 16 (I/O through I/O ) is written into the location specified on the Complementary metal oxide semiconductor (CMOS) for 8 15 address pins (A through A ). optimum speed and power 0 16 Reading from the device is accomplished by asserting Chip Byte power-down feature Enable (CE) and Output Enable (OE) LOW while forcing the Offered in Pb-free 48-ball very fine-pitch ball grid array Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then (VFBGA) and 44-pin thin small outline package (TSOP II) data from the memory location specified by the address pins package appears on I/O to I/O . If Byte High Enable (BHE) is LOW, then 0 7 data from memory appears on I/O to I/O . See the Truth Table 8 15 on page 11 for a complete description of read and write modes. Functional Description The CY62137EV30 is available in 48-ball VFBGA and 44-pin The CY62137EV30 is a high performance CMOS static RAM TSOPII packages. organized as 128K words by 16 bits. This device features For a complete list of related documentation, click here. advanced circuit design to provide ultra low active current. This Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 A 128K x 16 5 A 4 RAM Array I/O I/O 0 7 A 3 I/O I/O A 8 15 2 A 1 A 0 COLUMN DECODER BHE CE WE Power -Down CE Circuit BHE OE BLE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05443 Rev. *I Revised November 24, 2015 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 SENSE AMPS CY62137EV30 MoBL Contents Pin Configurations ...........................................................3 Ordering Information ...................................................... 12 Product Portfolio ..............................................................3 Ordering Code Definitions ......................................... 12 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 13 Operating Range ...............................................................4 Acronyms ........................................................................15 Electrical Characteristics .................................................4 Document Conventions ................................................. 15 Capacitance ......................................................................5 Units of Measure ....................................................... 15 Thermal Resistance ..........................................................5 Document History Page ................................................. 16 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 18 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 18 Data Retention Waveform ................................................6 Products ....................................................................18 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 18 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 18 Truth Table ......................................................................11 Technical Support ..................................................... 18 Document Number: 38-05443 Rev. *I Page 2 of 18