CY62137EV30LL-45ZSXIT Infineon

CY62137EV30 MoBL 2-Mbit (128 K 16) Static RAM 2-Mbit (128 K 16) Static RAM advanced circuit design to provide ultra low active current. This Features is ideal for providing More Battery Life (MoBL ) in portable applications such as cellular telephones. The device also has an Very high speed: 45 ns automatic power down feature that significantly reduces power Wide voltage range: 2.20 V to 3.60 V consumption by 90% when addresses are not toggling. The device can also be put into standby mode reducing power Pin compatible with CY62137CV30 consumption when deselected (CE HIGH or both BLE and BHE Ultra low standby power are HIGH). The input and output pins (I/O through I/O ) are 0 15 placed in a high impedance state when: deselected (CE HIGH), Typical standby current: 1 A outputs are disabled (OE HIGH), both Byte High Enable and Byte Maximum standby current: 7 A Low Enable are disabled (BHE, BLE HIGH), or during a write Ultra low active power operation (CE LOW and WE LOW). Typical active current: 2 mA at f = 1 MHz Writing to the device is accomplished by asserting Chip Enable Easy memory expansion with CE and OE features (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O through I/O ), is 0 7 Automatic power-down when deselected written into the location specified on the address pins (A through 0 A ). If Byte High Enable (BHE) is LOW, then data from I/O pins Complementary metal oxide semiconductor (CMOS) for 16 (I/O through I/O ) is written into the location specified on the optimum speed and power 8 15 address pins (A through A ). 0 16 Byte power-down feature Reading from the device is accomplished by asserting Chip Offered in Pb-free 48-ball very fine-pitch ball grid array Enable (CE) and Output Enable (OE) LOW while forcing the (VFBGA) and 44-pin thin small outline package (TSOP II) Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then package data from the memory location specified by the address pins appears on I/O to I/O . If Byte High Enable (BHE) is LOW, then 0 7 data from memory appears on I/O to I/O . See the Truth Table 8 15 Functional Description on page 11 for a complete description of read and write modes. The CY62137EV30 is a high performance CMOS static RAM The CY62137EV30 is available in 48-ball VFBGA and 44-pin organized as 128K words by 16 bits. This device features TSOPII packages. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 A 128K x 16 5 A 4 RAM Array I/O I/O 0 7 A 3 I/O I/O A 8 15 2 A 1 A 0 COLUMN DECODER BHE CE WE Power -Down CE Circuit BHE OE BLE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05443 Rev. *G Revised August 21, 2013 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 SENSE AMPS CY62137EV30 MoBL Contents Pin Configurations ...........................................................3 Ordering Information ...................................................... 12 Product Portfolio ..............................................................3 Ordering Code Definitions ......................................... 12 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 13 Operating Range ...............................................................4 Acronyms ........................................................................15 Electrical Characteristics .................................................4 Document Conventions ................................................. 15 Capacitance ......................................................................5 Units of Measure ....................................................... 15 Thermal Resistance ..........................................................5 Document History Page ................................................. 16 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 18 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 18 Data Retention Waveform ................................................6 Products ....................................................................18 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 18 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 18 Truth Table ......................................................................11 Technical Support ..................................................... 18 Document Number: 38-05443 Rev. *G Page 2 of 18