CY62137FV30 MoBL Automotive 2-Mbit (128 K 16) Static RAM 2-Mbit (128 K 16) Static RAM Features Functional Description Very high speed: 45 ns The CY62137FV30 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features Temperature ranges advanced circuit design to provide ultra low active current. This Automotive-A: 40 C to +85 C is ideal for providing More Battery Life (MoBL ) in portable Automotive-E: 40 C to +125 C applications such as cellular telephones. The device also has an Wide voltage range: 2.20 V3.60 V automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the Pin compatible with CY62137CV/CV25/CV30/CV33, device into standby mode reduces power consumption by more CY62137V, and CY62137EV30 than 99% when deselected (CE HIGH or both BLE and BHE are Ultra low standby power HIGH). The input and output pins (I/O through I/O ) are placed 0 15 Typical standby current: 1 A (Automotive-A) in a high impedance state in the following conditions when the Maximum standby current: 5 A (Automotive-A) device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both the Byte High Enable and the Byte Low Enable are Ultra low active power disabled (BHE, BLE HIGH), or during an active write operation Typical active current: 1.6 mA at f = 1 MHz (45 ns speed) (CE LOW and WE LOW). Easy memory expansion with CE and OE features Write to the device by taking Chip Enable (CE) and Write Enable Automatic power down when deselected (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O through I/O ) is written into the location 0 7 Complementary metal oxide semiconductor (CMOS) for specified on the address pins (A through A ). If Byte High 0 16 optimum speed and power Enable (BHE) is LOW, then data from I/O pins (I/O through 8 Byte power down feature I/O ) is written into the location specified on the address pins 15 (A through A ). 0 16 Available in 44-pin thin small outline package (TSOP) II Read from the device by taking Chip Enable (CE) and Output package Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O to I/O . If 0 7 Byte High Enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 11 for a 8 15 complete description of read and write modes. For a complete list of related resources, click here. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 128K x 16 6 A 5 I/O I/O RAM Array 0 7 A 4 A 3 I/O I/O 8 15 A 2 A 1 A 0 BHE COLUMN DECODER WE CE CE POWER DOWN OE CIRCUIT BHE BLE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-66190 Rev. *E Revised January 3, 2018 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 SENSE AMPS CY62137FV30 MoBL Automotive Contents Product Portfolio .............................................................. 3 Ordering Information ...................................................... 12 Pin Configuration .............................................................3 Ordering Code Definitions ......................................... 12 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 13 Operating Range ...............................................................4 Acronyms ........................................................................14 Electrical Characteristics .................................................4 Document Conventions ................................................. 14 Capacitance ......................................................................5 Units of Measure ....................................................... 14 Thermal Resistance ..........................................................5 Document History Page ................................................. 15 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 16 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 16 Data Retention Waveform ................................................6 Products ....................................................................16 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 16 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 16 Truth Table ......................................................................11 Technical Support ..................................................... 16 Document Number: 001-66190 Rev. *E Page 2 of 16