Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY62138F MoBL 2-Mbit (256K 8) Static RAM 2-Mbit (256K 8) Static RAM Features Functional Description High speed: 45 ns The CY62138F is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features Wide voltage range: 4.5 V to 5.5 V advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life (MoBL ) in portable Pin compatible with CY62138V applications. The device also has an automatic power down Ultra low standby power feature that significantly reduces power consumption when Typical standby current: 1 A addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when Maximum standby current: 5 A deselected (CE HIGH or CE LOW). 1 2 Ultra low active power To write to the device, take Chip Enable (CE LOW and CE 1 2 Typical active current: 1.6 mA f = 1 MHz HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O Easy memory expansion with CE , CE , and OE features pins (I/O through I/O ) is then written into the location specified 1 2 0 7 on the address pins (A through A ). 0 17 Automatic power down when deselected To read from the device, take Chip Enable (CE LOW and CE 1 2 Complementary metal oxide semiconductor (CMOS) for HIGH) and output enable (OE) LOW while forcing Write Enable optimum speed and power (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. Available in Pb-free 32-pin SOIC and 32-pin thin small outline package (TSOP) II packages The eight input and output pins (I/O through I/O ) are placed in 0 7 a high impedance state when the device is deselected (CE 1 HIGH or CE LOW), the outputs are disabled (OE HIGH), or 2 during a write operation (CE LOW and CE HIGH and WE 1 2 LOW). The CY62138F device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. For a complete list of related documentation, click here. Logic Block Diagram Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-13194 Rev. *N Revised March 29, 2019