CY62146ESL-45ZSXI Infineon

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62146ESL MoBL 4-Mbit (256K 16) Static RAM 4-Mbit (256K 16) Static RAM Features Functional Description Very high speed: 45 ns The CY62146ESL is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life (MoBL ) in portable Ultra low standby power applications such as cellular telephones. The device also has an Typical Standby current: 2.5 A automatic power down feature that reduces power consumption Maximum Standby current: 7 A when addresses are not toggling. Placing the device into standby Ultra low active power mode reduces power consumption by more than 99% when deselected (CE HIGH). The input and output pins (I/O through Typical active current: 3.5 mA at f = 1 MHz 0 I/O ) are placed in a high impedance state when the device is 15 Easy memory expansion with CE and OE features deselected (CE HIGH), the outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, Automatic power down when deselected BLE HIGH) or during a write operation (CE LOW and WE LOW). Complementary metal oxide semiconductor (CMOS) for To write to the device, take Chip Enable (CE) and Write Enable optimum speed and power (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O through I/O ) is written into the location Available in Pb-free 44-pin thin small outline package (TSOP) II 0 7 specified on the address pins (A through A ). If Byte High package 0 17 Enable (BHE) is LOW, then data from I/O pins (I/O through 8 I/O ) is written into the location specified on the address pins 15 (A through A ). 0 17 To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O to I/O . If 0 7 Byte High Enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 11 for a 8 15 complete description of read and write modes. For a complete list of related documentation, click here. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 256K 16 A 5 I/O I/O 0 7 A RAM Array 4 A 3 I/O I/O 8 15 A 2 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-43142 Rev. *J Revised June 26, 2020 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 SENSE AMPS