CY62146EV30 MoBL 4-Mbit (256 K 16) Static RAM 4-Mbit (256 K 16) Static RAM advanced circuit design designed to provide an ultra low active Features current. Ultra low active current is ideal for providing More Battery Life (MoBL ) in portable applications such as cellular Very high speed: 45 ns telephones. The device also has an automatic power down Temperature ranges feature that significantly reduces power consumption by 80 Industrial: 40 C to +85 C percent when addresses are not toggling.The device can also be Automotive-A: 40 C to +85 C put into standby mode reducing power consumption by more than 99 percent when deselected (CE HIGH). The input and Wide voltage range: 2.20 V to 3.60 V output pins (I/O through I/O ) are placed in a high impedance 0 15 Pin compatible with CY62146DV30 state when the device is deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Ultra low standby power Enable are disabled (BHE, BLE HIGH), or a write operation is in Typical standby current: 1 A progress (CE LOW and WE LOW). Maximum standby current: 7 A To write to the device, take Chip Enable (CE) and Write Enable Ultra low active power (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O through I/O ) is written into the location Typical active current: 2 mA at f = 1 MHz 0 7 specified on the address pins (A through A ). If Byte High 0 17 Easy memory expansion with CE and OE features Enable (BHE) is LOW, then data from the I/O pins (I/O through 8 I/O ) is written into the location specified on the address pins 15 Automatic power down when deselected (A through A ). 0 17 Complementary metal oxide semiconductor (CMOS) for To read from the device, take Chip Enable (CE) and Output optimum speed and power Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory Available in a Pb-free 48-ball very fine ball grid array (VFBGA) location specified by the address pins appears on I/O to I/O . If and 44-pin TSOP II Packages 0 7 Byte High Enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 11 for a Functional Description 8 15 complete description of read and write modes. The CY62146EV30 is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features an Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 256K x 16 A 5 I/O I/O 0 7 A RAM Array 4 A 3 I/O I/O 8 15 A 2 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05567 Rev. *I Revised August 22, 2013 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 SENSE AMPS CY62146EV30 MoBL Contents Pin Configurations ...........................................................3 Ordering Information ...................................................... 12 Product Portfolio ..............................................................3 Ordering Code Definitions ......................................... 12 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 13 Operating Range ...............................................................4 Acronyms ........................................................................15 Electrical Characteristics .................................................4 Document Conventions ................................................. 15 Capacitance ......................................................................5 Units of Measure ....................................................... 15 Thermal Resistance ..........................................................5 Document History Page ................................................. 16 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 18 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 18 Data Retention Waveform ................................................6 Products ....................................................................18 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 18 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 18 Truth Table ......................................................................11 Technical Support ..................................................... 18 Document Number: 38-05567 Rev. *I Page 2 of 18