CY62146G/CY62146GE CY62146GSL/CY62146GESL MoBL 4-Mbit (256K words 16 bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words 16 bit) Static RAM with Error-Correcting Code (ECC) devices are accessed by asserting both chip enable inputs CE Features 1 as low and CE as HIGH. 2 High speed: 45 ns/55 ns Data writes are performed by asserting the Write Enable (WE) Ultra-low standby power input LOW, while providing the data on I/O through I/O and 0 15 address on A through A pins. The Byte High Enable (BHE) Typical standby current: 3.5 A 0 17 and Byte Low Enable (BLE) inputs control write operations to the Maximum standby current: 8.7 A upper and lower bytes of the specified memory location. BHE 1 Embedded ECC for single-bit error correction controls I/O through I/O and BLE controls I/O through I/O . 8 15 0 7 Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V Data reads are performed by asserting the Output Enable (OE) 1.0-V data retention input and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O through I/O ). 0 15 TTL-compatible inputs and outputs Byte accesses can be performed by asserting the required byte Error indication (ERR) pin to indicate 1-bit error detection and enable signal (BHE or BLE) to read either the upper byte or the correction lower byte of data from the specified address location. Pb-free 48-ball VFBGA and 44-pin TSOP II packages All I/Os (I/O through I/O ) are placed in a HI-Z state when the 0 15 device is deselected (CE HIGH for a single chip enable device Functional Description and CE HIGH/CE LOW for a dual chip enable device), or 1 2 control signals are deasserted (OE, BLE, BHE). CY62146G/CY62146GE and CY62146GSL/CY62146GESL are On the CY62146GE/CY62146GESL devices, the detection and high-performance CMOS low-power (MoBL) SRAM devices with correction of a single-bit error in the accessed location is embedded ECC. Both devices are offered in single and dual chip 2 indicated by the assertion of the ERR output (ERR = HIGH) . enable options and in multiple pin configurations. The See the Truth Table CY62146GE/CY62146GESL device includes an ERR pin that CY62146G/CY62146GE/CY62146GSL/CY62146GESL on signals an error-detection and correction event during a read 1 page 17 for a complete description of read and write modes. cycle. The CY62146GSL/CY62146GESL device supports a wide voltage range of 2.2 V3.6 V and 4.5 V5.5 V. The logic block diagrams are on page 2. Devices with a single chip enable input are accessed by asserting the chip enable (CE) input LOW. Dual chip enable Product Portfolio Power Dissipation Features and Options Operating I , (mA) CC 3 Standby, I (A) SB2 Product Range V Range (V) Speed (ns) (see the Pin CC f = f max Configurations 4 4 Typ Max Typ Max section) CY62146G(E)18 Industrial 1.65 V2.2 V 55 15 20 3.5 10 Single or dual CY62146G(E)30 Chip Enables 2.2 V3.6 V 45 15 20 3.5 8.7 CY62146G(E) 4.5 V5.5 V Optional ERR 5 CY62146G(E)SL 2.2 V3.6 V and pin 4.5 V5.5 V Notes 1. Datasheet specifications are not guaranteed for V in the range of 3.6 V to 4.5 V. CC 2. This device does not support automatic write-back on error detection. 3. The ERR pin is available only for devices which have ERR option E in the ordering code. Refer Ordering Information for details. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V2.2 V), CC CC V =3 V (for V range of 2.2 V3.6 V), and V = 5 V (for V range of 4.5 V5.5 V), T = 25 C. CC CC CC CC A 5. Datasheet specifications are not guaranteed for V in the range of 3.6 V to 4.5 V. CC Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-95420 Rev. *E Revised April 26, 2017CY62146G/CY62146GE CY62146GSL/CY62146GESL MoBL Logic Block Diagram CY62146G/CY62146GSL ECCENCODER INPUTBUFFER A0 A1 A2 A3 I/O I/O MEMORY 0 7 A4 ARRAY A5 I/O I/O 8 15 A6 A7 A8 A9 COLUMNDECODER BHE WE CE 2 OE CE 1 BLE Logic Block Diagram CY62146GE/CY62146GESL ECCENCODER INPUTBUFFER A0 A1 ERR A2 A3 I/O I/O MEMORY 0 7 A4 ARRAY I/O I/O A5 8 15 A6 A7 A8 A9 COLUMNDECODER BHE WE CE 2 CE 1 OE BLE Document Number: 001-95420 Rev. *E Page 2 of 22 ROWDECODER A10 ROWDECODER A11 A12 A13 A10 A14 A11 A15 A12 A16 A13 A17 A14 A15 SENSE A16 A17 AMPLIFIERS SENSE ECCDECODER AMPLIFIERS ECCDECODER