CY62147EV18 MoBL 4-Mbit (256 K 16) Static RAM 4-Mbit (256 K 16) Static RAM is ideal for providing More Battery Life (MoBL ) in portable Features applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power Very high speed: 55 ns consumption when addresses are not toggling. Placing the Wide voltage range: 1.65 V to 2.25 V device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are Pin compatible with CY62147DV18 HIGH). The input and output pins (I/O through I/O ) are placed 0 15 Ultra low standby power in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both the Byte High Typical standby current: 1 A Enable and the Byte Low Enable are disabled (BHE, BLE HIGH), Maximum standby current: 7 A or during an active write operation (CE LOW and WE LOW). Ultra low active power To write to the device, take Chip Enable (CE) and Write Enable Typical active current: 2 mA at f = 1 MHz (WE) inputs LOW. If Byte Low Enable (BLE) is LOW then data Ultra low standby power from I/O pins (I/O through I/O ) is written into the location 0 7 specified on the address pins (A through A ). If Byte High 0 17 Easy memory expansion with CE and OE features Enable (BHE) is LOW, then data from I/O pins (I/O through 8 I/O ) is written into the location specified on the address pins Automatic power down when deselected 15 (A through A ). 0 17 Complementary metal oxide semiconductor (CMOS) for To read from the device, take Chip Enable (CE) and Output optimum speed and power Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Available in a Pb-free 48-ball very fine ball grid array (VFBGA) Byte Low Enable (BLE) is LOW, then data from the memory package location specified by the address pins apears on I/O to I/O . If 0 7 Byte High Enable (BHE) is LOW, then data from memory Functional Description appears on I/O to I/O . See the Truth Table on page 11 for a 8 15 complete description of read and write modes. The CY62147EV18 is a high performance CMOS static RAM For a complete list of related documentation, click here. organized as 256 K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 256K x 16 A 5 I/O I/O 0 7 A RAM Array 4 A 3 I/O I/O 8 15 A 2 A 1 A 0 COLUMN DECODER BHE CE POWER DOWN WE BHE CIRCUIT CE BLE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05441 Rev. *L Revised November 23, 2015 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 SENSE AMPS CY62147EV18 MoBL Contents Product Portfolio ..............................................................3 Ordering Information ...................................................... 12 Pin Configuration .............................................................3 Ordering Code Definitions ......................................... 12 Maximum Ratings .............................................................4 Package Diagram ............................................................ 13 Operating Range ...............................................................4 Acronyms ........................................................................14 Electrical Characteristics .................................................4 Document Conventions ................................................. 14 Capacitance ......................................................................5 Units of Measure ....................................................... 14 Thermal Resistance ..........................................................5 Document History Page ................................................. 15 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 17 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 17 Data Retention Waveform ................................................6 Products ....................................................................17 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 17 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 17 Truth Table ......................................................................11 Technical Support ..................................................... 17 Document Number: 38-05441 Rev. *L Page 2 of 17