Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62147EV30 MoBL 4-Mbit (256K 16) Static RAM 4-Mbit (256K 16) Static RAM portable applications such as cellular telephones. The device Features also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Very high speed: 45 ns Placing the device into standby mode reduces power Temperature ranges consumption by more than 99 percent when deselected (CE Industrial: 40 C to +85 C HIGH or both BLE and BHE are HIGH). The input and output pins Wide voltage range: 2.20 V to 3.60 V (I/O through I/O ) are placed in a high impedance state when: 0 15 Pin compatible with CY62147DV30 Deselected (CE HIGH) Ultra low standby power Outputs are disabled (OE HIGH) Typical standby current: 2.5 A Maximum standby current: 7 A (Industrial) Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) Ultra low active power Typical active current: 3.5 mA at f = 1 MHz Write operation is active (CE LOW and WE LOW) 1 Easy memory expansion with CE and OE features To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data Automatic power-down when deselected from I/O pins (I/O through I/O ) is written into the location 0 7 Complementary metal oxide semiconductor (CMOS) for specified on the address pins (A through A ). If Byte High 0 17 optimum speed and power Enable (BHE) is LOW, then data from I/O pins (I/O through 8 I/O ) is written into the location specified on the address pins 15 Available in Pb-free 48-ball very fine ball grid array (VFBGA) (A through A ). 0 17 (single/dual CE option) and 44-pin thin small outline package To read from the device, take Chip Enable (CE) and Output (TSOP) II packages Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte power-down feature Byte Low enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O to I/O . If 0 7 Functional Description Byte High enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 11 for a complete The CY62147EV30 is a high performance CMOS static RAM 8 15 description of read and write modes. (SRAM) organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active For a complete list of related documentation, click here. current. It is ideal for providing More Battery Life (MoBL ) in Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 256K x 16 A 5 I/O I/O 0 7 A RAM Array 4 A 3 I/O I/O 8 15 A 2 A 1 A 0 COLUMN DECODER BHE CE POWER DOWN WE BHE 1 CIRCUIT CE BLE OE BLE Note 1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE and 1 CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH. 2 1 2 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05440 Rev. *T Revised June 26, 2020 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 SENSE AMPS