CY62147EV30LL-45ZSXIT Infineon

CY62147EV30 MoBL 4-Mbit (256 K 16) Static RAM 4-Mbit (256 K 16) Static RAM Features Functional Description Very high speed: 45 ns The CY62147EV30 is a high performance CMOS static RAM (SRAM) organized as 256 K words by 16 bits. This device Temperature ranges features advanced circuit design to provide ultra low active Industrial: 40 C to +85 C current. It is ideal for providing More Battery Life (MoBL ) in Wide voltage range: 2.20 V to 3.60 V portable applications such as cellular telephones. The device Pin compatible with CY62147DV30 also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Ultra low standby power Placing the device into standby mode reduces power Typical standby current: 1 A consumption by more than 99 percent when deselected (CE Maximum standby current: 7 A (Industrial) HIGH or both BLE and BHE are HIGH). The input and output pins Ultra low active power (I/O through I/O ) are placed in a high impedance state when: 0 15 Typical active current: 2 mA at f = 1 MHz Deselected (CE HIGH) 1 Easy memory expansion with CE and OE features Outputs are disabled (OE HIGH) Automatic power-down when deselected Both Byte High Enable and Byte Low Enable are disabled Complementary metal oxide semiconductor (CMOS) for (BHE, BLE HIGH) optimum speed and power Write operation is active (CE LOW and WE LOW) Available in Pb-free 48-ball very fine ball grid array (VFBGA) To write to the device, take Chip Enable (CE) and Write Enable (single/dual CE option) and 44-pin thin small outline package (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data (TSOP) II packages from I/O pins (I/O through I/O ) is written into the location 0 7 Byte power-down feature specified on the address pins (A through A ). If Byte High 0 17 Enable (BHE) is LOW, then data from I/O pins (I/O through 8 I/O ) is written into the location specified on the address pins 15 (A through A ). 0 17 To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O to I/O . If 0 7 Byte High enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 11 for a complete 8 15 description of read and write modes. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 256K x 16 A 5 I/O I/O 0 7 A RAM Array 4 A 3 I/O I/O 8 15 A 2 A 1 A 0 COLUMN DECODER BHE CE POWER DOWN WE BHE 1 CIRCUIT CE BLE OE BLE Note 1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE and 1 CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH. 2 1 2 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05440 Rev. *N Revised August 22, 2013 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 SENSE AMPS CY62147EV30 MoBL Contents Product Portfolio ..............................................................3 Ordering Information ...................................................... 12 Pin Configurations ...........................................................3 Ordering Code Definitions ......................................... 12 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 13 Operating Range ...............................................................4 Acronyms ........................................................................15 Electrical Characteristics .................................................4 Document Conventions ................................................. 15 Capacitance ......................................................................5 Units of Measure ....................................................... 15 Thermal Resistance ..........................................................5 Document History Page ................................................. 16 AC Test Load and Waveforms .........................................5 Sales, Solutions, and Legal Information ...................... 18 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 18 Data Retention Waveform ................................................6 Products ....................................................................18 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 18 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 18 Truth Table ......................................................................11 Technical Support ..................................................... 18 Document Number: 38-05440 Rev. *N Page 2 of 18