CY62147G/CY621472G MoBL Automotive 4-Mbit (256K words 16-bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words 16-bit) Static RAM with Error-Correcting Code (ECC) Data writes are performed by asserting the Write Enable (WE) Features input LOW, while providing the data on I/O through I/O and 0 15 High speed: 45 ns/55 ns address on A through A pins. The Byte High Enable (BHE) 0 17 and Byte Low Enable (BLE) inputs control write operations to the Temperature Ranges upper and lower bytes of the specified memory location. BHE Automotive-A: -40 C to +85 C Automotive-E: -40 C to +125 C controls I/O through I/O and BLE controls I/O through I/O . 8 15 0 7 Ultra-low standby power Data reads are performed by asserting the Output Enable (OE) Typical standby current: 3.5 A input and providing the required address on the address lines. 1, 2 Read data is accessible on the I/O lines (I/O through I/O ). Embedded ECC for single-bit error correction 0 15 Byte accesses can be performed by asserting the required byte Wide voltage range: 2.2 V to 3.6 V enable signal (BHE or BLE) to read either the upper byte or the 1.0-V data retention lower byte of data from the specified address location. TTL-compatible inputs and outputs All I/Os (I/O through I/O ) are placed in a HI-Z state when the 0 15 device is deselected (CE HIGH for a single chip enable device Pb-free 48-ball VFBGA and 44-pin TSOP II packages and CE HIGH/CE LOW for a dual chip enable device), or 1 2 Functional Description control signals are deasserted (OE, BLE, BHE). The device also has a unique Byte Power down feature, where, CY62147G/CY621472G is high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC. Both devices are if both the Byte Enables (BHE and BLE) are disabled, the offered in single and dual chip enable options and in multiple pin devices seamlessly switch to standby mode irrespective of the configurations. state of the chip enables, thereby saving power. Devices with a single chip enable input are accessed by The logic block diagrams are on page 2. asserting the chip enable (CE) input LOW. Dual chip enable devices are accessed by asserting both chip enable inputs CE 1 as low and CE as HIGH. 2 Notes 1. This device does not support automatic write-back on error detection. 2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-95424 Rev. *E Revised April 2, 2018CY62147G/CY621472G MoBL Automotive Logic Block Diagram CY62147G ECCENCODER INPUTBUFFER A0 A1 A2 A3 I/O I/O MEMORY 0 7 A4 ARRAY A5 I/O I/O 8 15 A6 A7 A8 A9 COLUMNDECODER BHE WE CE OE BLE Logic Block Diagram CY621472G ECCENCODER INPUTBUFFER A0 A1 A2 A3 I/O I/O 0 7 MEMORY A4 ARRAY I/O I/O A5 8 15 A6 A7 A8 A9 COLUMNDECODER BHE WE CE 2 OE CE 1 BLE Document Number: 001-95424 Rev. *E Page 2 of 20 ROWDECODER ROWDECODER A10 A10 A11 A11 A12 A12 A13 A13 A14 A14 A15 A15 A16 A16 A17 A17 SENSE SENSE AMPLIFIERS AMPLIFIERS ECCDECODER ECCDECODER