CY62147GN/CY621472GN MoBL 4-Mbit (256K words 16 bit) Static RAM 4-Mbit (256K words 16 bit) Static RAM Features Functional Description High speed: 45 ns/55 ns CY62147GN and CY621472GN are high-performance CMOS low-power (MoBL) SRAM devices organized as 256K Words by Ultra-low standby power 16-bits. Both devices are offered in single and dual chip enable Typical standby current: 3.5 A options and in multiple pin configurations. Maximum standby current: 8.7 A Devices with a single chip enable input are accessed by Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V asserting the chip enable (CE) input LOW. Dual chip enable 1.0-V data retention devices are accessed by asserting both chip enable inputs CE 1 as low and CE as HIGH. 2 TTL-compatible inputs and outputs Data writes are performed by asserting the Write Enable (WE) Pb-free 48-ball VFBGA and 44-pin TSOP II packages input LOW, while providing the data on I/O through I/O and 0 15 address on A through A pins. The Byte High Enable (BHE) 0 17 and Byte Low Enable (BLE) inputs control write operations to the upper and lower bytes of the specified memory location. BHE controls I/O through I/O and BLE controls I/O through I/O . 8 15 0 7 Data reads are performed by asserting the Output Enable (OE) input and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O through I/O ). 0 15 Byte accesses can be performed by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O through I/O ) are placed in a HI-Z state when the 0 15 device is deselected (CE HIGH for a single chip enable device and CE HIGH/CE LOW for a dual chip enable device), or 1 2 control signals are de-asserted (OE, BLE, BHE). The device also has a unique Byte Power down feature, where, if both the Byte Enables (BHE and BLE) are disabled, the devices seamlessly switch to standby mode irrespective of the state of the chip enables, thereby saving power. The logic block diagram is provided in page 2. Product Portfolio Power Dissipation Features and Options Operating I , (mA) CC Standby, I (A) SB2 Product Range V Range (V) Speed (ns) (see the Pin CC f = f max Configurations 1 1 Typ Max Typ Max section) CY62147GN18 Industrial 1.65 V2.2 V 55 15 20 3.5 10 Single or dual Chip Enables CY62147GN30 2.2 V3.6 V 45 15 20 3.5 8.7 CY621472GN30 CY62147GN 4.5 V5.5 V Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V2.2 V), CC CC V =3 V (for V range of 2.2 V3.6 V), and V = 5 V (for V range of 4.5 V5.5 V), T = 25 C. CC CC CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-10624 Rev. *D Revised December 21, 2017 CY62147GN/CY621472GN MoBL Logic Block Diagram CY62147GN INPUTBUFFER A0 A1 A2 A3 I/O I/O 0 7 MEMORY A4 ARRAY I/O I/O A5 8 15 A6 A7 A8 A9 COLUMNDECODER BHE WE CE 2 CE OE 1 BLE Document Number: 002-10624 Rev. *D Page 2 of 20 ROWDECODER A10 A11 A12 A13 A14 A15 A16 A17 SENSE AMPLIFIERS