Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62148E MoBL 4-Mbit (512K 8) Static RAM 4-Mbit (512K 8) Static RAM advanced circuit design to provide ultra low standby current. This Features is ideal for providing More Battery Life (MoBL ) in portable applications. The device also has an automatic power-down Very high speed: 45 ns feature that significantly reduces power consumption when Voltage range: 4.5 V to 5.5 V addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when Pin compatible with CY62148B deselected (CE HIGH). The eight input and output pins (I/O 0 Ultra low standby power through I/O ) are placed in a high impedance state when the 7 device is deselected (CE HIGH), Outputs are disabled (OE Typical standby current: 2.5 A HIGH), or during an active Write operation (CE LOW and WE Maximum standby current: 7 A (Industrial) LOW). Ultra low active power To write to the device, take Chip Enable (CE) and Write Enable Typical active current: 3.5 mA at f = 1 MHz (WE) inputs LOW. Data on the eight I/O pins (I/O through I/O ) 0 7 Easy memory expansion with CE, and OE features is then written into the location specified on the address pins (A 0 through A ). 18 Automatic power-down when deselected To read from the device, take Chip Enable (CE) and Output Complementary metal oxide semiconductor (CMOS) for Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under optimum speed and power these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. Available in Pb-free 32-pin thin small outline package (TSOP) II 1 and 32-pin small-outline integrated circuit (SOIC) packages The CY62148E device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that Functional Description require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. The CY62148E is a high performance CMOS static RAM For a complete list of related documentation, click here. organized as 512K words by 8-bits. This device features Logic Block Diagram A 0 I/O INPUT BUFFER IO 0 0 A 1 A 2 I/O 1 IO 1 A 3 A I/O 4 2 IO 2 A 5 A I/O 6 512K x 8 IO 3 3 A 7 A I/O 8 4 ARRAY IO 4 A 9 A I/O 10 5 IO 5 A 11 A I/O 12 6 IO 6 CE I/O 7 POWER IO 7 COLUMN DECODER DOWN WE OE Note 1. SOIC package is available only in 55 ns speed bin. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05442 Rev. *S Revised June 26, 2020 ROW DECODER A 13 A 14 A 15 A 16 A 17 A 18 SENSE AMPS