Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62148ESL MoBL 4-Mbit (512K 8) Static RAM 4-Mbit (512K 8) Static RAM Features Functional Description Higher speed up to 55 ns The CY62148ESL is a high performance CMOS static RAM organized as 512K words by 8-bits. This device features Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life (MoBL ) in portable Ultra low standby power applications. The device also has an automatic power-down Typical standby current: 2.5 A feature that significantly reduces power consumption. Placing Maximum standby current: 7 A the device in standby mode reduces power consumption by Ultra low active power more than 99 percent when deselected (CE HIGH). The eight input and output pins (I/O through I/O ) are placed in a high Typical active current: 3.5 mA at f = 1 MHz 0 7 impedance state when the device is deselected (CE HIGH), the Easy memory expansion with CE and OE features outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). Automatic power-down when deselected To write to the device, take Chip Enable (CE) and Write Enable Complementary metal oxide semiconductor (CMOS) for (WE) inputs LOW. Data on the eight I/O pins (I/O through I/O ) 0 7 optimum speed and power is then written into the location specified on the address pins (A 0 through A ). Available in Pb-free 32-pin shrunk thin small outline package 18 (STSOP) package To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The CY62148ESL device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. For a complete list of related resources, click here. Logic Block Diagram A 0 I/O INPUT BUFFER IO 0 0 A 1 A 2 I/O IO 1 1 A 3 A 4 I/O IO 2 2 A 5 A I/O 6 3 512K x 8 IO 3 A 7 A I/O 8 4 ARRAY IO 4 A 9 A I/O 10 5 IO 5 A 11 A I/O 12 6 IO 6 CE I/O 7 POWER IO 7 COLUMN DECODER WE DOWN OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-50045 Rev. *K Revised June 26, 2020 ROW DECODER A 13 A 14 A 15 A 16 A 17 A 18 SENSE AMPS