Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY62157ESL MoBL 8-Mbit (512K 16) Static RAM 8-Mbit (512K 16) Static RAM addresses are not toggling. Place the device into standby mode Features when deselected (CE HIGH or both BHE and BLE are HIGH). The input or output pins (I/O through I/O ) are placed in a high Very high speed: 45 ns 0 15 impedance state when the device is deselected (CE HIGH), the Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V outputs are disabled (OE HIGH), both the Byte High Enable and the Byte Low Enable are disabled (BHE, BLE HIGH), or during Ultra low standby power an active write operation (CE LOW and WE LOW). Typical Standby current: 2 A To write to the device, take Chip Enable (CE) and Write Enable Maximum Standby current: 8 A (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data Ultra low active power from I/O pins (I/O through I/O ) is written into the location 0 7 Typical active current: 1.8 mA at f = 1 MHz specified on the address pins (A through A ). If Byte High 0 18 Enable (BHE) is LOW, then data from I/O pins (I/O through 8 Easy memory expansion with CE and OE features I/O ) is written into the location specified on the address pins 15 Automatic power down when deselected (A through A ). 0 18 To read from the device, take Chip Enable (CE) and Output Complementary metal oxide semiconductor (CMOS) for Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If optimum speed and power Byte Low Enable (BLE) is LOW, then data from the memory Available in Pb-free 44-pin thin small outline package (TSOP) II location specified by the address pins appear on I/O to I/O . If 0 7 package Byte High Enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 11 for a 8 15 Functional Description complete description of read and write modes. The CY62157ESL device is suitable for interfacing with The CY62157ESL is a high performance CMOS static RAM processors that have TTL I/P levels. It is not suitable for organized as 512K words by 16 bits. This device features processors that require CMOS I/P levels. Please see Electrical advanced circuit design to provide ultra low active current. This Characteristics on page 4 for more details and suggested is ideal for providing More Battery Life (MoBL ) in portable alternatives. applications. The device also has an automatic power down feature that significantly reduces power consumption when For a complete list of related documentation, click here. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 512K 16 A 5 RAM Array I/O I/O A 0 7 4 A 3 I/O I/O 8 15 A 2 A 1 A 0 COLUMN DECODER CE Power Down BHE WE Circuit BHE CE BLE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-43141 Rev. *J Revised April 1, 2019 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 SENSE AMPS