Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62157EV30 MoBL 8-Mbit (512K 16) Static RAM 8-Mbit (512K 16) Static RAM Features Functional Description Thin small outline package (TSOP) I package configurable as The CY62157EV30 is a high performance CMOS static RAM 512K 16 or 1M 8 static RAM (SRAM) organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This High speed: 45 ns is ideal for providing More Battery Life (MoBL ) in portable applications such as cellular telephones. The device also has an Temperature ranges automatic power down feature that significantly reduces power Industrial: 40 C to +85 C consumption when addresses are not toggling. Place the device Automotive-A: 40 C to +85 C into standby mode when deselected (CE HIGH or CE LOW or 1 2 Automotive-E: 40 C to +125 C both BHE and BLE are HIGH). The input or output pins (I/O 0 through I/O ) are placed in a high impedance state when the Wide voltage range: 2.20 V to 3.60 V 15 device is deselected (CE HIGH or CE LOW), the outputs are 1 2 Pin compatible with CY62157DV30 disabled (OE HIGH), Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or a write operation is active (CE Ultra low standby power 1 LOW, CE HIGH and WE LOW). 2 Typical standby current: 2 A To write to the device, take Chip Enable (CE LOW and CE Maximum standby current: 8 A (Industrial) 1 2 HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable Ultra low active power (BLE) is LOW, then data from I/O pins (I/O through I/O ) is 0 7 Typical active current: 6 mA at f = 1 MHz written into the location specified on the address pins (A through 0 A ). If Byte High Enable (BHE) is LOW, then data from I/O pins 18 Easy memory expansion with CE , CE , and OE features 1 2 (I/O through I/O ) is written into the location specified on the 8 15 Automatic power down when deselected address pins (A through A ). 0 18 To read from the device, take Chip Enable (CE LOW and CE Complementary Metal Oxide Semiconductor (CMOS) for 1 2 HIGH) and Output Enable (OE) LOW while forcing the Write optimum speed and power Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data Available in Pb-free and non Pb-free 48-ball very fine-pitch ball from the memory location specified by the address pins appear grid array (VFBGA), Pb-free 44-pin thin small outline package on I/O to I/O . If Byte High Enable (BHE) is LOW, then data from 0 7 (TSOP) II and 48-pin TSOP I packages memory appears on I/O to I/O . See Truth Table on page 13 8 15 for a complete description of read and write modes. For a complete list of related documentation, click here. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 512K 16/1M 8 A 5 RAM Array I/O I/O 0 7 A 4 A I/O I/O 3 8 15 A 2 A 1 A 0 COLUMN DECODER BYTE CE 2 BHE CE 1 Power Down WE CE 2 Circuit CE BHE 1 OE BLE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05445 Rev. *S Revised February 28, 2020 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 SENSE AMPS