Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62157G/CY62157GE MoBL 8-Mbit (512K 16-bits) Static RAM with Error-Correcting Code (ECC) CY62157G/CY62157GE MoBL, 8-Mbit (512K 16-bits) Static RAM with Error-Correcting Code (ECC) Features Functional Description Ultra-low standby current CY62157G and CY62157GE are high-performance CMOS low-power (MoBL ) SRAM device with Embedded Typical standby current: 1.4 A Error-Correcting Code. ECC logic can detect and correct single Maximum standby current: 6.5 A bit error in accessed location. High speed: 45 ns This device is offered in dual chip enable option. Dual chip Voltage range: 1.65 V to 3.6 V enable devices are accessed by asserting both chip enable inputs CE as LOW and CE as HIGH. 1 2 Embedded Error-Correcting Code (ECC) for single-bit error Data writes are performed by asserting the Write Enable input correction (WE LOW), and providing the data and address on device data 1.0 V data retention (I/O through I/O ) and address (A through A ) pins 0 15 0 18 respectively. The Byte High/Low Enable (BHE, BLE) inputs Transistor-transistor logic (TTL) compatible inputs and outputs control byte writes, and write data on the corresponding I/O lines Available in Pb-free 48-ball VFBGA, 44-TSOP II and 48-pin to the memory location specified. BHE controls I/O through 8 TSOP I packages I/O and BLE controls I/O through I/O . 15 0 7 Data reads are performed by asserting the Output Enable (OE) input and providing the required address on the address lines. Read data is accessible on I/O lines (I/O through I/O ). Byte 0 15 accesses can be performed by asserting the required byte enable signal (BHE, BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O through I/O ) are placed in a high impedance state 0 15 when the device is deselected (CE HIGH/CE LOW for dual 1 2 chip enable device), or control signals are de-asserted (OE, BLE, BHE). These devices also have a unique Byte Power down feature, where, if both the Byte Enables (BHE and BLE) are disabled, the devices seamlessly switch to standby mode irrespective of the state of the chip enable(s), thereby saving power. The CY62157G and CY62157GE devices are available in a Pb-free 48-ball VFBGA, 44-TSOP II and 48-pin TSOP I packages. See the Logic Block Diagram CY62157G on page 2. The device in the 48-pin TSOP I package can also be configured to function as a 1M 8-bit device. See the Pin Configurations on page 5. Product Portfolio Power Dissipation Operating I , (mA) CC Product Range V Range (V) Speed (ns) Standby, I (A) CC SB2 f = f max 1 1 Typ Max Typ Max CY62157G18 Industrial 1.65 V2.2 V 55 18 22 2.0 8 CY62157G30 Industrial 2.2 V3.6 V 45 18 25 1.4 6.5 Note 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V =3V (for V range of 2.2 V3.6 V) and CC CC V = 1.8V (for V range of 1.65 V2.2 V), T = 25 C. CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-27323 Rev. *C Revised February 28, 2020