Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY62158G/CY62158GE MoBL 8-Mbit (1M 8-bits) Static RAM with Error-Correcting Code (ECC) CY62158G/CY62158GE MoBL, 8-Mbit (1M 8-bits) Static RAM with Error-Correcting Code (ECC) Features Functional Description Ultra-low standby power CY62158G/CY62158GE is a high-performance CMOS low-power (MoBL) SRAM device with embedded ECC. Typical standby current: 1.4 A Maximum standby current: 6.5 A Device is accessed by asserting both chip enable inputs CE 1 as LOW and CE as HIGH. 2 High speed: 45 ns Write to the device is performed by taking Chip Enable 1 (CE ) 1 Embedded error-correcting code (ECC) for single-bit error LOW and Chip Enable 2 (CE ) HIGH and the Write Enable (WE) 2 1, 2 correction input LOW. Data on the eight I/O pins (I/O through I/O ) is then 0 7 written into the location specified on the address pins (A through 0 Operating voltage range: 2.2 V to 3.6 V A ). 19 1.0-V data retention Read from the device is performed by taking Chip Enable 1 (CE ) 1 Transistor-transistor logic (TTL) compatible inputs and outputs and Output Enable (OE) LOW and Chip Enable 2 (CE ) HIGH 2 while forcing Write Enable (WE) HIGH. Under these conditions, Available in Pb-free 48-ball VFBGA and 44-pin TSOP II the contents of the memory location specified by the address package pins will appear on the I/O pins. The eight input and output pins (I/O through I/O ) are placed in 0 7 a high-impedance state when the device is deselected (CE 1 HIGH or CE LOW), the outputs are disabled (OE HIGH), or a 2 write operation is in progress (CE LOW and CE HIGH and WE 1 2 LOW). See the Truth Table CY62158G/CY62158GE on page 13 for a complete description of read and write modes. Product Portfolio Power Dissipation Operating I CC Features and Options V Range Speed (mA) CC Product (see Pin Configurations Range Standby I (A) SB2 (V) (ns) CY62158G) f = f max 3 3 Typ Max Typ Max CY62158G/CY62158GE Dual Chip Enable Industrial 2.2 V3.6 V 45 18 25 1.46.5 Notes 1. This device does not support automatic write-back on error detection. 2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3V (for V range of 2.2V - 3.6V), T = 25 C. CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-29691 Rev. *A Revised February 28, 2020