Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY62167E MoBL 16-Mbit (1 M 16 / 2 M 8) Static RAM 16-Mbit (1 M 16 / 2 M 8) Static RAM and BLE are HIGH). The input and output pins (I/O through Features 0 I/O ) are placed in a high impedance state when: 15 Configurable as 1 M 16 or as 2 M 8 SRAM The device is deselected (CE HIGH or CE LOW) 1 2 Very high speed: 45 ns Outputs are disabled (OE HIGH) Wide voltage range: 4.5 V to 5.5 V Both byte high enable and byte low enable are disabled (BHE, BLE HIGH) or Ultra low standby power Typical standby current: 1.5 A A write operation is in progress (CE LOW, CE HIGH, and WE 1 2 Maximum standby current: 12 A LOW) Ultra low active power To write to the device, take chip enables (CE LOW and CE 1 2 HIGH) and write enable (WE) input LOW. If byte low enable Typical active current: 2.2 mA at f = 1 MHz (BLE) is LOW, then data from I/O pins (I/O through I/O ), is 0 7 Easy memory expansion with CE , CE , and OE features 1 2 written into the location specified on the address pins (A through 0 A ). If byte high enable (BHE) is LOW, then data from the I/O Automatic power-down when deselected 19 pins (I/O through I/O ) is written into the location specified on 8 15 CMOS for optimum speed and power the address pins (A through A ). 0 19 Offered in 48-pin TSOP I package To read from the device, take chip enables (CE LOW and CE 1 2 HIGH) and output enable (OE) LOW while forcing the write Functional Description enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins appears The CY62167E is a high performance CMOS static RAM on I/O to I/O . If byte high enable (BHE) is LOW, then data from 0 7 organized as 1 M words by 16-bits/2 M words by 8-bits. This memory appears on I/O to I/O . See Truth Table on page 12 8 15 device features advanced circuit design to provide an ultra low for a complete description of read and write modes. active current. This is ideal for providing More Battery Life The CY62167E device is suitable for interfacing with processors (MoBL ) in portable applications. The device also has an that have TTL I/P levels. It is not suitable for processors that automatic power down feature that reduces power consumption require CMOS I/P levels. Please see Electrical Characteristics when addresses are not toggling. Place the device into standby on page 4 for more details and suggested alternatives. mode when deselected (CE HIGH, or CE LOW, or both BHE 1 2 For a complete list of related documentation, click here. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 1 M 16 / 2 M 8 A 5 I/O I/O 0 7 RAM ARRAY A 4 A I/O I/O 3 8 15 A 2 A 1 A 0 COLUMN DECODER BYTE BHE CE 2 WE CE 2 CE 1 POWER DOWN CE 1 CIRCUIT OE BHE BLE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-15607 Rev. *G Revised July 20, 2015 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 SENSE AMPS