CY62167G30/CY62167GE30 16-Mbit (1M words 16-bit/ 2M words 8-bit) Static RAM with Error-Correcting Code (ECC) CY62167G30/CY62167GE30, 16-Mbit (1M words 16-bit/2M words 8-bit) Static RAM with Error-Correcting Code (ECC) through I/O ) and address pins (A through A ) respectively. Features 15 0 19 The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs Ultra-low standby current control byte writes and write data on the corresponding I/O lines Typical standby current: 1.5 A to the memory location specified. BHE controls I/O through 8 Maximum standby current: 8 A I/O and BLE controls I/O through I/O . 15 0 7 High speed: 45 ns To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. You can Embedded error-correcting code (ECC) for single-bit error 1 access read data on the I/O lines (I/O through I/O ). To perform 0 15 correction byte accesses, assert the required byte enable signal (BHE or Operating voltage range: 2.2 V to 3.6 V BLE) to read either the upper byte or the lower byte of data from the specified address location. 1.0-V data retention All I/Os (I/O through I/O ) are placed in a high-impedance state 0 15 Transistor-transistor logic (TTL) compatible inputs and outputs when the device is deselected (CE HIGH for a single chip enable Error indication (ERR) pin to indicate 1-bit error detection and device and CE HIGH/CE LOW for a dual chip enable device), 1 2 correction or the control signals are de-asserted (OE, BLE, BHE). 48-pin TSOP I package configurable as 1M 16 or 2M 8 These devices have a unique Byte Power-down feature where, SRAM if both the Byte Enables (BHE and BLE) are disabled, the devices seamlessly switch to the standby mode irrespective of Available in Pb-free 48-ball VFBGA and 48-pin TSOP I the state of the chip enables, thereby saving power. packages On the CY62167GE30 devices, the detection and correction of Functional Description a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = High). See the Truth Table CY62167G30 and CY62167GE30 are high-performance CMOS, 2 CY62167G30/CY62167GE30 on page 15 for a complete low-power (MoBL ) SRAM devices with embedded ECC . Both description of read and write modes. devices are offered in single and dual chip enable options and in multiple pin configurations. The CY62167GE30 device includes The CY62167G30 and CY62167GE30 devices are available in an ERR pin that signals a single-bit error-detection and a Pb-free 48-pin TSOP I package and 48-ball VFBGA packages. correction event during a read cycle. See the Logic Block Diagram CY62167G30 on page 2. To access devices with a single chip enable input, assert the chip The device in the 48-pin TSOP I package can also be configured enable (CE) input LOW. To access dual chip enable devices, to function as a 2M words 8 bit device. Refer to the Pin assert both chip enable inputs CE as LOW and CE as HIGH. Configurations section for details. 1 2 To perform data writes, assert the Write Enable (WE) input LOW, For a complete list of related documentation, click here. and provide the data and address on the device data pins (I/O 0 Product Portfolio Current Consumption Features and Options Operating I , (mA) Standby, I (A) CC SB2 Product (see the Pin Range V Range (V) Speed (ns) CC f = f Configurations max 5 Typ Max 5 section) Typ Max CY62167G30/ Single or Dual Chip Industrial 2.2 V3.6 V 45 29 35 1.5 8 3, 4 CY62167GE30 Enables Optional ERR pin Notes 1. SER FIT rate <0.1 FIT/Mb. Refer to AN88889 for details. 2. This device does not support automatic write-back on error detection. 3. This device offers improved I , I and I specifications compared to the previous revision with same marketing part number. CC SB1 SB2 4. For previous version of this device, kindly refer here. Further details about improvement and comparison between old and new versions can be found in the PIN193805. 5. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V =3V (for V range of 2.2 V3.6 V), T = 25 C. CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-20054 Rev. *F Revised March 18, 2020CY62167G30/CY62167GE30 Logic Block Diagram CY62167G30 ECC ENCODE DATA DRIVERS IN A0 A1 A2 1M x 16 / A3 I/O -I/O 0 7 A4 2M x 8 A5 I/O -I/O 8 15 RAM ARRAY A6 A7 A8 A9 COLUMN DECODER CE BYTE POWER DOWN BHE CIRCUIT BHE WE CE 2 BLE OE CE 1 BLE Logic Block Diagram CY62167GE30 ECC ENCODE DATA DRIVERS IN A0 A1 A2 1M x 16 / ERR A3 A4 2M x 8 A5 I/O -I/O 0 7 RAM ARRAY A6 I/O -I/O 8 15 A7 A8 A9 COLUMN DECODER CE BYTE POWER DOWN BHE CIRCUIT BHE WE CE 2 BLE OE CE 1 BLE Document Number: 002-20054 Rev. *F Page 2 of 21 ROW DECODER ROW DECODER A10 A11 A10 A12 A11 A13 A12 A14 A13 A15 A14 A16 A15 A17 A16 A18 A17 A19 A18 A19 SENSE AMPS SENSE AMPS ECC DECODE ECC DECODE