CY62167G Automotive 16-Mbit (1M Words 16-Bit) Static RAM with Error-Correcting Code (ECC) 16-Mbit (1M Words 16-Bit) Static RAM with Error-Correcting Code (ECC) Data writes are performed by asserting the Write Enable input Features (WE) LOW, and providing the data and address on device data (I/O through I/O ) and address (A through A ) pins AEC-Q100 qualified 0 15 0 19 respectively. The Byte High/Low Enable (BHE, BLE) inputs Ultra-low standby power control byte writes, and write data on the corresponding I/O lines Typical standby current: 5.5 A to the memory location specified. BHE controls I/O through 8 Maximum standby current: 75 A I/O BLE controls I/O through I/O . 15 0 7 High speed: 45 ns / 55 ns Data reads are performed by asserting the Output Enable (OE) input and providing the required address on the address lines. Embedded error-correcting code (ECC) for single-bit error Read data is accessible on I/O lines (I/O through I/O ). Byte 0 15 correction accesses can be performed by asserting the required byte Temperature Ranges: enable signal (BHE, BLE) to read either the upper byte or the lower byte of data from the specified address location. Automotive-A: -40 C to +85 C Automotive-E: -40 C to +125 C All I/Os (I/O through I/O ) are placed in a HI-Z state when the 0 15 device is deselected (CE HIGH / CE LOW for dual chip-enable 1 2 Operating voltage range: 2.2 V to 3.6 V device), or control signals are de-asserted (OE, BLE, and BHE). 1.0-V data retention These devices also have a unique Byte Power down feature TTL-compatible inputs and outputs where if both the Byte Enables (BHE and BLE) are disabled, the Available in Pb-free 48-ball VFBGA and 48-pin TSOPI devices seamlessly switches to standby mode irrespective of the packages state of the chip enable(s), thereby saving power. The CY62167G device is available in a Pb-free 48-ball VFBGA Functional Description and 48-pin TSOP I packages. The device in the 48-pin TSOP I package can also be configured to function as a 2M words 8 CY62167G is high-performance CMOS low-power (MoBL) bit device.The logic block diagram is on page 2. Refer to Pin SRAM devices with embedded ECC. This device is offered in Configurations on page 4 and the associated footnotes for dual chip-enable. details. Devices with dual chip-enable are accessed by asserting both chip-enable inputs CE as LOW and CE as HIGH. 1 2 Note 1. This device does not support automatic write-back on error detection. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-84902 Rev. *F Revised May 3, 2017CY62167G Automotive Logic Block Diagram CY62167G ECC ENCODE DATA DRIVERS IN A0 A1 A2 1M x 16 / A3 I/O -I/O 0 7 A4 2M x 8 A5 I/O -I/O 8 15 RAM ARRAY A6 A7 A8 A9 COLUMN DECODER CE BYTE POWER DOWN BHE CIRCUIT BHE WE CE 2 BLE OE CE 1 BLE Document Number: 001-84902 Rev. *F Page 2 of 19 ROW DECODER A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 SENSE AMPS ECC DECODE