CY62167G/CY62167GE MoBL 16-Mbit (1M words 16-bit/2M words 8-bit) Static RAM with Error-Correcting Code (ECC) 16-Mbit (1M words 16-bit/2M words 8-bit) Static RAM with Error-Correcting Code (ECC) through I/O ) and address pins (A through A ) respectively. Features 15 0 19 The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs Ultra-low standby current control byte writes and write data on the corresponding I/O lines Typical standby current: 5.5 A to the memory location specified. BHE controls I/O through 8 Maximum standby current: 16 A I/O and BLE controls I/O through I/O . 15 0 7 High speed: 45 ns/55 ns To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. You can Embedded error-correcting code (ECC) for single-bit error access read data on the I/O lines (I/O through I/O ). To perform 0 15 correction byte accesses, assert the required byte enable signal (BHE or Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and BLE) to read either the upper byte or the lower byte of data from 4.5 V to 5.5 V the specified address location. 1.0-V data retention All I/Os (I/O through I/O ) are placed in a high-impedance state 0 15 when the device is deselected (CE HIGH for a single chip enable Transistor-transistor logic (TTL) compatible inputs and outputs device and CE HIGH / CE LOW for a dual chip enable device), 1 2 Error indication (ERR) pin to indicate 1-bit error detection and or the control signals are de-asserted (OE, BLE, BHE). correction These devices have a unique Byte Power-down feature where, 48-pin TSOP I package configurable as 1M 16 or 2M 8 if both the Byte Enables (BHE and BLE) are disabled, the SRAM devices seamlessly switch to the standby mode irrespective of the state of the chip enables, thereby saving power. Available in Pb-free 48-ball VFBGA and 48-pin TSOPI packages On the CY62167GE devices, the detection and correction of a single-bit error in the accessed location is indicated by the Functional Description assertion of the ERR output (ERR = High). See the Truth Table CY62167G/CY62167GE on page 16 for a complete description CY62167G and CY62167GE are high-performance CMOS, 1 of read and write modes. low-power (MoBL ) SRAM devices with embedded ECC . Both devices are offered in single and dual chip enable options and in The CY62167G and CY62167GE devices are available in a multiple pin configurations. The CY62167GE device includes an Pb-free 48-pin TSOP I package and 48-ball VFBGA packages. ERR pin that signals a single-bit error-detection and correction The logic block diagrams are on page 2. event during a read cycle. The device in the 48-pin TSOP I package can also be configured To access devices with a single chip enable input, assert the chip to function as a 2M words 8-bit device. Refer to the Pin enable (CE) input LOW. To access dual chip enable devices, Configurations section for details. assert both chip enable inputs CE as LOW and CE as HIGH. 1 2 For a complete list of related documentation, click here. To perform data writes, assert the Write Enable (WE) input LOW, and provide the data and address on the device data pins (I/O 0 Product Portfolio Current Consumption Features and Options Operating I , (mA) CC Standby, I (A) SB2 Product Range V Range (V) Speed (ns) (see the Pin CC f = f max Configurations 2 2 Typ Max Typ Max section) CY62167G(E)18 Single or dual Industrial 1.65 V2.2 V 55 29 32 7 26 Chip Enables CY62167G(E)30 2.2 V3.6 V 45 29 36 5.5 16 Optional ERR pin CY62167G(E) 4.5 V5.5 V Notes 1. This device does not support automatic write-back on error detection. 2. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V2.2 V), V =3 V CC CC CC (for V range of 2.2 V3.6 V), and V = 5 V (for V range of 4.5 V5.5 V), T = 25 C. CC CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-81537 Rev. *P Revised May 26, 2017 CY62167G/CY62167GE MoBL Logic Block Diagram CY62167G ECC ENCODE DATA DRIVERS IN A0 A1 A2 1M x 16 / A3 I/O -I/O 0 7 A4 2M x 8 A5 I/O -I/O 8 15 RAM ARRAY A6 A7 A8 A9 COLUMN DECODER CE BYTE POWER DOWN BHE CIRCUIT BHE WE CE 2 BLE OE CE 1 BLE Logic Block Diagram CY62167GE ECC ENCODE DATA DRIVERS IN A0 A1 A2 1M x 16 / ERR A3 A4 2M x 8 A5 I/O -I/O 0 7 RAM ARRAY A6 I/O -I/O 8 15 A7 A8 A9 COLUMN DECODER CE BYTE POWER DOWN BHE CIRCUIT BHE WE CE 2 BLE OE CE 1 BLE Document Number: 001-81537 Rev. *P Page 2 of 23 ROW DECODER ROW DECODER A10 A11 A10 A12 A11 A13 A12 A14 A13 A15 A14 A16 A15 A17 A16 A18 A17 A19 A18 A19 SENSE AMPS SENSE AMPS ECC DECODE ECC DECODE