Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62167G/CY62167GE MoBL 16-Mbit (1M words 16-bit/ 2M words 8-bit) Static RAM with Error-Correcting Code (ECC) CY62167G/CY62167GE MoBL, 16-Mbit (1M words 16-bit/2M words 8-bit) Static RAM with Error-Correcting Code (ECC) through I/O ) and address pins (A through A ) respectively. Features 15 0 19 The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs Ultra-low standby current control byte writes and write data on the corresponding I/O lines Typical standby current: 5.5 A to the memory location specified. BHE controls I/O through 8 Maximum standby current: 16 A I/O and BLE controls I/O through I/O . 15 0 7 High speed: 45 ns/55 ns To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. You can Embedded error-correcting code (ECC) for single-bit error access read data on the I/O lines (I/O through I/O ). To perform 0 15 correction byte accesses, assert the required byte enable signal (BHE or Wide voltage range: 1.65 V to 2.2 V, and 4.5 V to 5.5 V BLE) to read either the upper byte or the lower byte of data from the specified address location. 1.0-V data retention All I/Os (I/O through I/O ) are placed in a high-impedance state 0 15 Transistor-transistor logic (TTL) compatible inputs and outputs when the device is deselected (CE HIGH for a single chip enable Error indication (ERR) pin to indicate 1-bit error detection and device and CE HIGH / CE LOW for a dual chip enable device), 1 2 correction or the control signals are de-asserted (OE, BLE, BHE). 48-pin TSOP I package configurable as 1M 16 or 2M 8 These devices have a unique Byte Power-down feature where, SRAM if both the Byte Enables (BHE and BLE) are disabled, the devices seamlessly switch to the standby mode irrespective of Available in Pb-free 48-ball VFBGA and 48-pin TSOP I the state of the chip enables, thereby saving power. packages On the CY62167GE devices, the detection and correction of a Functional Description single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = High). See the Truth Table CY62167G and CY62167GE are high-performance CMOS, 1 CY62167G/CY62167GE on page 16 for a complete description low-power (MoBL ) SRAM devices with embedded ECC . Both of read and write modes. devices are offered in single and dual chip enable options and in multiple pin configurations. The CY62167GE device includes an The CY62167G and CY62167GE devices are available in a ERR pin that signals a single-bit error-detection and correction Pb-free 48-pin TSOP I package and 48-ball VFBGA packages. event during a read cycle. The logic block diagrams are on page 2. To access devices with a single chip enable input, assert the chip The device in the 48-pin TSOP I package can also be configured enable (CE) input LOW. To access dual chip enable devices, to function as a 2M words 8-bit device. Refer to the Pin assert both chip enable inputs CE as LOW and CE as HIGH. Configurations section for details. 1 2 To perform data writes, assert the Write Enable (WE) input LOW, For a complete list of related documentation, click here. and provide the data and address on the device data pins (I/O 0 Product Portfolio Current Consumption Features and Options (see the Operating I , (mA) V Range Speed CC CC Product Range Standby, I (A) SB2 (V) (ns) Pin Configurations f = f max section) 2 2 Typ Max Typ Max CY62167G(E)18 Single or Dual Chip Industrial 1.65 V2.2 V 55 29 32 7 26 Enables CY62167G(E) 4.5 V5.5 V 45 29 36 5.5 16 Optional ERR pin Notes 1. This device does not support automatic write-back on error detection. 2. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V2.2 V), and CC CC V = 5 V (for V range of 4.5 V5.5 V), T = 25 C. CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-81537 Rev. *R Revised February 7, 2020