CY62167GN MoBL 16-Mbit (1M 16/2M 8) Static RAM 16-Mbit (1M 16/2M 8) Static RAM Features Functional Description Ultra-low standby power The CY62167GN is a high performance CMOS static RAM organized as 1M words by 16 bits or 2M words by 8 bits. This Typical standby current: 5.5 A device features an advanced circuit design that provides an ultra Maximum standby current: 16 A low active current. Ultra low active current is ideal for providing TSOP I package configurable as 1M 16 or 2M 8 SRAM More Battery Life (MoBL ) in portable applications such as cellular telephones. The device also has an automatic power Very high speed: 45 ns down feature that reduces power consumption by 99 percent Temperature ranges when addresses are not toggling. Place the device into standby mode when deselected (CE HIGH or CE LOW or both BHE and Industrial: 40 C to +85 C 1 2 BLE are HIGH). The input and output pins (I/O through I/O ) 0 15 Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V are placed in a high impedance state when: the device is to 5.5 V deselected (CE HIGH or CE LOW), outputs are disabled (OE 1 2 HIGH), both Byte High Enable and Byte Low Enable are disabled Easy memory expansion with CE , CE , and OE Features 1 2 (BHE, BLE HIGH), or a write operation is in progress (CE LOW, 1 Automatic power-down when deselected CE HIGH and WE LOW). 2 CMOS for optimum speed and power To write to the device, take Chip Enables (CE LOW and CE 1 2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable Offered in Pb-free 48-ball VFBGA and 48-pin TSOP I packages (BLE) is LOW, then data from I/O pins (I/O through I/O ) is 0 7 written into the location specified on the address pins (A through 0 A ). If Byte High Enable (BHE) is LOW, then data from the I/O 19 pins (I/O through I/O ) is written into the location specified on 8 15 the address pins (A through A ). 0 19 To read from the device, take Chip Enables (CE LOW and CE 1 2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O to I/O . If Byte High Enable (BHE) is LOW, then data from 0 7 memory appears on I/O to I/O . See Truth Table on page 13 8 15 for a complete description of read and write modes. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 1M 16/2M 8 6 A 5 RAM Array I/O I/O 0 7 A 4 A I/O I/O 3 8 15 A 2 A 1 A 0 COLUMN DECODER BYTE BHE CE 2 WE CE 2 CE 1 Power Down CE 1 OE Circuit BHE BLE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-93628 Rev. *D Revised June 23, 2017 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 SENSE AMPS CY62167GN MoBL Contents Pin Configuration .............................................................3 Ordering Information ...................................................... 14 Product Portfolio ..............................................................3 Ordering Code Definitions ......................................... 14 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 15 Operating Range ...............................................................4 Acronyms ........................................................................17 Electrical Characteristics .................................................4 Document Conventions ................................................. 17 Capacitance ......................................................................6 Units of Measure ....................................................... 17 Thermal Resistance ..........................................................6 Document History Page ................................................. 18 AC Test Loads and Waveforms .......................................6 Sales, Solutions, and Legal Information ...................... 19 Data Retention Characteristics .......................................7 Worldwide Sales and Design Support ....................... 19 Data Retention Waveform ................................................7 Products ....................................................................19 Switching Characteristics ................................................8 PSoC Solutions ...................................................... 19 Switching Waveforms ......................................................9 Cypress Developer Community ................................. 19 Truth Table ......................................................................13 Technical Support ..................................................... 19 Document Number: 001-93628 Rev. *D Page 2 of 19