CY62168EV30 MoBL 16-Mbit (2M 8) Static RAM 16-Mbit (2M 8) Static RAM Features Functional Description Very high speed: 45 ns The CY62168EV30 is a high performance CMOS static RAM organized as 2M words by 8-bits. This device features advanced Wide voltage range: 2.20 V to 3.60 V circuit design to provide an ultra low active current. This is ideal for providing More Battery Life (MoBL ) in portable Ultra low standby power applications such as cellular telephones. The device also has an Typical standby current: 1.5 A automatic power-down feature that significantly reduces power Maximum standby current: 12 A consumption by 90% when addresses are not toggling. Placing Ultra low active power the device into standby mode reduces power consumption by more than 99% when deselected (Chip Enable 1 (CE ) HIGH or Typical active current: 7 mA at f = 1 MHz 1 Chip Enable 2 (CE ) LOW). The input and output pins (I/O 2 0 Easy memory expansion with CE , CE and OE features 1 2 through I/O ) are placed in a high impedance state when: the 7 device is deselected (Chip Enable 1 (CE ) HIGH or 1 Automatic power-down when deselected Chip Enable 2 (CE ) LOW), outputs are disabled (OE HIGH), or 2 CMOS for optimum speed/power a write operation is in progress (Chip Enable 1 (CE ) LOW and 1 Chip Enable 2 (CE ) HIGH and WE LOW). 2 Offered in Pb-free 48-ball FBGA package. For Pb-free 48-pin Write to the device by taking Chip Enable 1 (CE ) LOW and TSOP I package, refer to CY62167EV30 data sheet. 1 Chip Enable 2 (CE ) HIGH and the Write Enable (WE) input 2 LOW. Data on the eight I/O pins (I/O through I/O ) is then written 0 7 into the location specified on the address pins (A through A ). 0 20 Read from the device by taking Chip Enable 1 (CE ) and 1 Output Enable (OE) LOW and Chip Enable 2 (CE ) HIGH while 2 forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input and output pins (I/O through I/O ) are placed in 0 7 a high impedance state when the device is deselected (CE 1 HIGH or CE LOW), the outputs are disabled (OE HIGH), or a 2 write operation is in progress (CE LOW and CE HIGH and WE 1 2 LOW). See the Truth Table on page 12 for a complete description of read and write modes. For a complete list of related documentation, click here. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-07721 Rev. *K Revised August 29, 2018 CY62168EV30 MoBL Logic Block Diagram A 0 DATA IN DRIVERS I/O 0 A 1 A 2 I/O 1 A 3 A 4 I/O 2 A 5 A 6 2M x 8 I/O 3 A 7 A 8 ARRAY I/O 4 A 9 A 10 I/O 5 A 11 A 12 I/O 6 CE 1 POWER I/O CE 7 2 COLUMN DECODER DOWN WE OE Document Number: 001-07721 Rev. *K Page 2 of 19 ROW DECODER A 13 A 14 A 15 A 16 A 17 A 18 A 19 A 20 SENSE AMPS