Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62177EV30 MoBL 32-Mbit (2M 16/4M 8) Static RAM 32-Mbit (2M 16/4M 8) Static RAM Features Functional Description Thin small outline package TSOP I configurable as 2M 16 or The CY62177EV30 is a high performance CMOS static RAM as 4M 8 static RAM (SRAM) organized as 2M words by 16 bits and 4M words by 8 bits. This device features advanced circuit design to provide ultra low Very high speed active current. It is ideal for providing More Battery Life 55 ns (MoBL ) in portable applications such as cellular telephones. The device also has an automatic power down feature that Wide voltage range significantly reduces power consumption by 99 percent when 2.2 V to 3.6 V addresses are not toggling. The device can also be put into Ultra low standby power standby mode when deselected (CE HIGH or CE LOW or both 1 2 BHE and BLE are HIGH). The input and output pins (I/O through Typical standby current: 3 A 0 I/O ) are placed in a high impedance state when: deselected 15 Maximum standby current: 25 A (CE HIGH or CE LOW), outputs are disabled (OE HIGH), both 1 2 Ultra low active power Byte High Enable and Byte Low Enable are disabled (BHE, BLE Typical active current: 10 mA at f = 1 MHz HIGH), or during a write operation (CE LOW, CE HIGH and WE 1 2 LOW). Easy memory expansion with CE , CE and OE Features 1 2, To write to the device, take Chip Enables (CE LOW and CE 1 2 Automatic power down when deselected HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O through I/O ), is 0 7 Complementary Metal Oxide Semiconductor (CMOS) for written into the location specified on the address pins (A through 0 optimum speed and power A ). If Byte High Enable (BHE) is LOW, then data from I/O pins 20 Available in Pb-free 48-pin TSOP I package and 48-ball FBGA (I/O through I/O ) is written to the location specified on the 8 15 package address pins (A through A ). To read from the device, take 0 20 Chip Enables (CE LOW and CE HIGH) and Output Enable 1 2 (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O to I/O . If Byte High 0 7 Enable (BHE) is LOW, then data from memory appears on I/O 8 to I/O . See the Truth Table on page 11 for a complete 15 description of read and write modes. Pin 13 of the 48 TSOP I package is an DNU pin that must be left floating at all times to ensure proper application. For a complete list of related resources, click here. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 2M 16 A 5 I/O I/O RAM Array 0 7 A 4 A I/O I/O 3 8 15 A 2 A 1 A 0 COLUMN DECODER BYTE BHE WE CE 2 CE 1 OE BLE Power-Down Circuit BHE CE 2 CE BLE 1 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-09880 Rev. *Q Revised October 6, 2019 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 A 20 SENSE AMPS