CY62187EV30 MoBL 64-Mbit (4 M 16) Static RAM 64-Mbit (4 M 16) Static RAM Features Functional Description Very high speed The CY62187EV30 is a high performance CMOS static RAM organized as 4 M words by 16-bits. This device features 55 ns advanced circuit design to provide ultra low active current. It is Wide voltage range ideal for providing More Battery Life (MoBL ) in portable 2.2 V to 3.7 V applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power Ultra low standby power consumption by 99 percent when addresses are not toggling. Typical standby current: 8 A The device can also be put into standby mode when deselected Maximum standby current: 48 A (CE HIGH or CE LOW or both BHE and BLE are HIGH). The 1 2 input and output pins (I/O through I/O ) are placed in a high Ultra low active power 0 15 impedance state when: deselected (CE HIGH or CE LOW), 1 2 Typical active current: 7.5 mA at f = 1 MHz outputs are disabled (OE HIGH), both Byte High Enable and Easy memory expansion with CE , CE and OE features Byte Low Enable are disabled (BHE, BLE HIGH), or during a 1 2, write operation (CE LOW, CE HIGH and WE LOW). 1 2 Automatic power down when deselected To write to the device, take Chip Enables (CE LOW and CE 1 2 CMOS for optimum speed and power HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O through I/O ), is 0 7 Available in Pb-free 48-ball FBGA package written into the location specified on the address pins (A through 0 A ). If Byte High Enable (BHE) is LOW, then data from I/O pins 21 (I/O through I/O ) is written into the location specified on the 8 15 address pins (A through A ). 0 21 To read from the device, take Chip Enables (CE LOW and CE 1 2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O to I/O . If Byte High Enable (BHE) is LOW, then data from 0 7 memory appears on I/O to I/O . See the Truth Table on page 8 15 9 for a complete description of read and write modes. For a complete list of related documentation, click here. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-48998 Rev. *L Revised November 9, 2017 CY62187EV30 MoBL Logic Block Diagram DATA-IN DRIVERS A 10 A 9 A 8 A 7 A 4096K 16 6 A 5 RAM Array I/O I/O 0 7 A 4 A I/O I/O 3 8 15 A 2 A 1 A 0 COLUMN DECODER BHE WE CE 2 CE 1 OE BLE Power down Circuit Document Number: 001-48998 Rev. *L Page 2 of 19 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 A 20 A 21 SENSE AMPS