Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY62187G30 MoBL 64-Mbit (4M words 16-bit) Static RAM with Error-Correcting Code (ECC) CY62187G30 MoBL, 64-Mbit (4M words 16-bit) Static RAM with Error-Correcting Code (ECC) To perform data writes, assert the Write Enable (WE) input LOW, Features and provide the data and address on the device data pins (I/O 0 Ultra-low standby current through I/O ) and address pins (A through A ) respectively. 15 0 21 Typical standby current: 6 A The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs Maximum standby current: 38 A control byte writes and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O through 8 High speed: 55 ns I/O and BLE controls I/O through I/O . 15 0 7 Embedded error-correcting code (ECC) for single-bit error 1 To perform data reads, assert the Output Enable (OE) input and correction provide the required address on the address lines. You can Operating voltage range: 2.2 V to 3.6 V access the read data on the I/O lines (I/O through I/O ). To 0 15 perform byte accesses, assert the required byte enable signal 1.0-V data retention (BHE or BLE) to read either the upper byte or the lower byte of Transistor-transistor logic (TTL) compatible inputs and outputs the data from the specified address location. Error indication (ERR) pin to indicate 1-bit error detection and All I/Os (I/O through I/O ) are placed in a High-Z state when 0 15 correction the device is deselected (CE HIGH / CE LOW for a Dual Chip 1 2 Enable device), or the control signals are deasserted (OE, BLE, Available in Pb-free 48-ball VFBGA package BHE). Functional Description These devices have a unique byte power-down feature where, when both Byte Enables (BHE and BLE) are disabled, the CY62187G30 is a high-performance CMOS, low-power (MoBL ) 2 devices seamlessly switch to the standby mode irrespective of SRAM device with embedded ECC . This device is offered in the state of the Chip Enables, thereby saving power. Dual Chip Enable option. CY62187G30 is available in a Pb-free 48-ball VFBGA package. To access a Dual Chip Enable device, assert both Chip Enable See Logic Block Diagram CY62187G30 on page 2. inputs CE as LOW and CE as HIGH. 1 2 For a complete list of related documentation, click here. Product Portfolio Current Consumption Features and Options Operating I , (mA) Standby, I (A) CC SB2 Product Range V Range (V) Speed (ns) (see Pin Configuration CC f = f max CY62187G30) 3 3 Typ Max Typ Max CY62187G30 Dual Chip Enable Industrial 2.2 V3.6 V 55 40 55 6 38 Notes 1. SER FIT rate <0.1 FIT/Mb. Refer to AN88889 for details. 2. This device does not support automatic write-back on error detection. 3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V =3V (for V range of 2.2 V3.6 V), T = 25C. CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-24731 Rev. *B Revised May 28, 2020