Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62256N 256-Kbit (32 K 8) Static RAM 256-Kbit (32 K 8) Static RA Features Functional Description Temperature ranges The CY62256N is a high performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is Commercial: 0 C to +70 C provided by an active LOW chip enable (CE) and active LOW Industrial: 40 C to +85 C output enable (OE) and tristate drivers. This device has an Automotive-A: 40 C to +85 C automatic power-down feature, reducing the power consumption Automotive-E: 40 C to +125 C by 99.9 percent when deselected. High speed: 55 ns An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE Voltage range: 4.5 V to 5.5 V operation inputs are both LOW, data on the eight data input/output pins Low active power (I/O through I/O ) is written into the memory location addressed 0 7 by the address present on the address pins (A through A ). 275 mW (max) 0 14 Reading the device is accomplished by selecting the device and Low standby power (LL version) enabling the outputs, CE and OE active LOW, while WE remains 82.5 W (max) inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are Easy memory expansion with CE and OE Features present on the eight data input/output pins. TTL-compatible inputs and outputs The input/output pins remain in a high impedance state unless the chip is selected, outputs are enabled, and write enable (WE) Automatic power-down when deselected is HIGH. CMOS for optimum speed and power For a complete list of related documentation, click here. Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP, 28-pin (300-mil) narrow SOIC, 28-pin TSOP I, and 28-pin reverse TSOP I packages Logic Block Diagram I/O 0 INPUTBUFFER I/O 1 A 10 A 9 I/O 2 A 8 A 7 A I/O 3 6 32K x 8 A 5 ARRAY A I/O 4 4 A 3 A 2 I/O 5 CE I/O 6 POWER WE COLUMN DOWN DECODER I/O 7 OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-06511 Rev. *J Revised April 28, 2017 ROW DECODER A 14 A 13 A 12 A 11 A 1 A 0 SENSE AMPS