CY7C008V CY7C018V CY7C009V CY7C019V 3.3 V, 128K 8 Dual-Port Static RAM CY7C009V 3.3 V, 128K 8 Dual-Port Static RAM 3.3 V, 128K 8 Dual-Port Static RAM Expandable data bus to 16 bits or more using Master/Slave Features chip select when using more than one device True dual-ported memory cells which allow simultaneous On-chip arbitration logic access of the same memory location Semaphores included to permit software handshaking 128K 8 organization (CY7C009) between ports 0.35-micron CMOS for optimum speed/power INT flag for port-to-port communication High-speed access: 15/20/25 ns Dual chip enables Low operating power Pin select for Master or Slave Active: I = 115 mA (typical) CC Commercial and industrial temperature ranges Standby: I = 10 A (typical) SB3 Available in 100-pin TQFP Fully asynchronous operation Pb-free packages available Automatic power-down Logic Block Diagram R/W R/W L R CE CE 0L 0R CE CE CE CE 1L 1R L R OE OE L R 8 8 I/O I/O I/O I/O 0L 8L 0R 8R I/O I/O Control Control 17 17 Address Address True Dual-Ported A A A A 0L 16L 0R 16R RAM Array Decode Decode 17 17 A A A A 0L 16L 0R 16R CE CE Interrupt L R OE Semaphore OE L R Arbitration R/W R/W L R SEM SEM L R 1 1 BUSY BUSY L R INT INT L R M/S Note 1. BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06044 Rev. *J Revised December 21, 2017CY7C009V Each port has independent control pins: chip enable (CE), read Functional Description or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the The CY7C009V is a low-power CMOS 64K, 128K 8 dual-port port is trying to access the same location currently being static RAM. Various arbitration schemes are included on the accessed by the other port. The interrupt flag (INT) permits devices to handle situations when multiple processors access communication between ports or systems by means of a mail the same piece of data. Two ports are provided permitting box. The semaphores are used to pass a flag, or token, from one independent, asynchronous access for reads and writes to any port to the other to indicate that a shared resource is in use. The location in memory. The devices can be utilized as standalone semaphore logic is comprised of eight shared latches. Only one 8/9-bit dual-port static RAMs or multiple devices can be side can control the latch (semaphore) at any time. Control of a combined in order to function as a 16/18-bit or wider semaphore indicates that a shared resource is in use. An master/slave dual-port static RAM. An M/S pin is provided for automatic power-down feature is controlled independently on implementing 16/18-bit or wider memory applications without the each port by a chip select (CE) pin. need for separate master and slave devices or additional discrete logic. Application areas include The CY7C009V is available in 100-pin Thin Quad Plastic interprocessor/multiprocessor designs, communications status Flatpacks (TQFP). buffering, and dual-port video/graphics memory. For a complete list of related documentation, click here. Document Number: 38-06044 Rev. *J Page 2 of 23