CY7C024E
CY7C025E
CY7C0251E
4 K 16 and 8 K 16/18
Dual-Port Static RAM with SEM, INT, BUSY
Features Functional Description
True dual-ported memory cells that allow simultaneous reads The CY7C024E and CY7C025E/CY7C0251E are low-power
of the same memory location CMOS 4K 16 and 8K 16/18 dual-port static RAMs. Various
arbitration schemes are included on the CY7C024E and
4 K 16 organization (CY7C024E)
CY7C025E/CY7C0251E to handle situations when multiple
processors access the same piece of data. Two ports are
8 K 16 organization (CY7C025E)
provided, permitting independent, asynchronous access for
8 K 18 organization (CY7C0251E)
reads and writes to any location in memory. The CY7C024E and
CY7C025E/CY7C0251E can be used as standalone 16 or 18-bit
0.35- complementary metal oxide semiconductor (CMOS) for
dual-port static RAMs or multiple devices can be combined to
optimum speed and power
function as a 32-/36-bit or wider master/ slave dual-port static
High-speed access: 15 ns RAM. An M/S pin is provided for implementing 32-/36-bit or wider
memory applications without the need for separate master and
Low operating power: I = 180 mA (typ), I = 0.05 mA (typ)
CC SB3
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
Fully asynchronous operation
status buffering, and dual-port video/graphics memory.
Automatic power-down
Each port has independent control pins: Chip Enable (CE), Read
Expandable data bus to 32/36 bits or more using master/slave or Write Enable (R/W), and Output Enable (OE). Two flags are
chip select when using more than one device provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
On-chip arbitration logic
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a mail
Semaphores included to permit software handshaking
box. The semaphores are used to pass a flag, or token, from one
between ports
port to the other to indicate that a shared resource is in use. The
INT flag for port-to-port communication
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
Separate upper-byte and lower-byte control
semaphore indicates that a shared resource is in use. An
Pin select for master or slave automatic power-down feature is controlled independently on
each port by a CE pin.
Available in Pb-free 100-pin thin quad flatpack (TQFP) package
The CY7C024E and CY7C025E/CY7C0251E are available in
100-pin Pb-free TQFP.
For a complete list of related documentation, click here.
Selection Guide
Parameter -15 -25 -55
Maximum access time (ns) 15 25 55
Typical operating current (mA) 190 170 150
Typical standby current for I(mA) 504020
SB1
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-62932 Rev. *G Revised November 26, 2014 CY7C024E
CY7C025E
CY7C0251E
Logic Block Diagram
R/W
L
R/W
R
UB
L
UB
R
LB
L LB
R
CE
L
CE
R
OE OE
L
R
[10]
[3]
I/O I/O I/O I/O
8L 15L 8R 15R
I/O I/O
CONTROL CONTROL
[9]
[2]
I/O I/O I/O I/O
0L 7L 0R 7R
[6] [1]
BUSY BUSY
L R
(CY7C025E/0251E) A A (CY7C025E/0251E)
12L 12R
MEMORY
A ADDRESS ADDRESS A
11L 11R
ARRAY
DECODER DECODER
A A
0L 0R
INTERRUPT
CE CE
L SEMAPHORE R
ARBITRATION
OE OE
L R
UB
UB R
L
LB
LB R
L
R/W
R/WL R
SEM SEM
R
L
INT M/S INT
L R
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. I/O I/O on the CY7C0251E.
0 8
3. I/O I/O on the CY7C0251E.
9 17
Document Number: 001-62932 Rev. *G Page 2 of 24