CY7C024/024A/0241 CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY Features Functional Description True dual-ported memory cells, which allow simultaneous The CY7C024/024A/0241 and CY7C025/0251 are low power reads of the same memory location CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the CY7C024/ 0241 and 1 4K x 16 organization (CY7C024/024A ) CY7C025/0251 to handle situations when multiple processors access the same piece of data. Two ports are provided, 4K x 18 organization (CY7C0241) permitting independent, asynchronous access for reads and 8K x 16 organization (CY7C025) writes to any location in memory. The CY7C024/ 0241 and CY7C025/0251 can be used as standalone 16 or 18-bit dual-port 8K x 18 organization (CY7C0251) static RAMs or multiple devices can be combined to function as 0.65 micron CMOS for optimum speed and power a 32-/36-bit or wider master/ slave dual-port static RAM. An M/S pin is provided for implementing 32-/36-bit or wider memory High speed access: 15 ns applications without the need for separate master and slave devices or additional discrete logic. Application areas include Low operating power: I = 150 mA (typ) CC interprocessor/multiprocessor designs, communications status Fully asynchronous operation buffering, and dual-port video/graphics memory. Automatic power down Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are Expandable data bus to 32/36 bits or more using Master/Slave provided on each port (BUSY and INT). BUSY signals that the chip select when using more than one device port is trying to access the same location currently being accessed by the other port. The Interrupt Flag (INT) permits On-chip arbitration logic communication between ports or systems by means of a mail Semaphores included to permit software handshaking box. The semaphores are used to pass a flag, or token, from one between ports port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one INT flag for port-to-port communication side can control the latch (semaphore) at any time. Control of a Separate upper-byte and lower-byte control semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on Pin select for Master or Slave each port by a chip select (CE) pin. Available in 84-pin (Pb-free) PLCC, 84-pin PLCC, 100-pin The CY7C024/024A/0241 and CY7C025/0251 are available in (Pb-free) TQFP, and 100-pin TQFP 84-pin Pb-free PLCCs, 84-pin PLCCs (CY7C024 and CY7C025 only), 100-pin Pb-free Thin Quad Plastic Flatplack (TQFP), and 100-pin Thin Quad Plastic Flatpack. Note 1. CY7C024 and CY7C024A are functionally identical. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-06035 Rev. *D Revised December 09, 2008 + Feedback CY7C024/024A/0241 CY7C025/0251 Logic Block Diagram R/W L R L UB R LB R L CE R OE L OE R 4 4 I/O I/O I/O I/O 8L 15L 8R 15R I/O I/O CONTROL CONTROL 3 3 I/O I/O I/O I/O 0L 7L 0R 7R 2 2 BUSY BUSY L R A (CY7C025/0251) (CY7C025/0251) A 12R 12L MEMORY A ADDRESS ADDRESS A 11L 11R ARRAY DECODER DECODER A A 0L 0R INTERRUPT CE CE L SEMAPHORE R ARBITRATION OE OE L R UB UB R L LB LB L R R/W R/W R L SEM SEM R L INT L M/S INT R Pin Configurations Figure 1. 84-Pin PLCC (Top View) 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 A 7L I/O 8L 12 73 A 6L I/O 9L 13 72 A 5L 14 I/O 10L 71 A 4L 15 I/O 11L 70 A 3L I/O 16 12L 69 A 2L I/O 17 13L 68 A 1L 18 GND 67 A 0L I/O 19 14L 66 INT L 20 I/O 15L BUSY 65 L V CY7C024/024A/025 CC 21 64 GND GND 22 M/S 63 23 I/O 0R BUSY 62 R 24 I/O 1R 61 INT R 25 I/O 2R A 60 0R V CC 26 A 59 1R I/O 3R 27 A 2R 58 I/O 4R 28 A 3R 57 I/O 5R 29 A 56 4R I/O 6R 30 A 55 5R I/O 7R 31 A 54 6R I/O 32 8R 33 34 35 36 37 38 39 40 41 42 43 44 45 46 48 49 50 51 52 53 47 Notes 2. BUSY is an output in master mode and an input in slave mode. 3. I/O I/O on the CY7C0241/0251. 0 8 4. I/O I/O on the CY7C0241/0251. 9 17 5. A on the CY7C025/0251. 12L 6. A on the CY7C025/0251. 12R Document : 38-06035 Rev. *D Page 2 of 21 + Feedback I/O 9R I/O 7L I/O 10R I/O 6L I/O 11R I/O 5L I/O 12R I/O 4L I/O 13R I/O 3L I/O 14R I/O 2L GND GND I/O 15R I/O 1L OE R I/O 0L R/W R OE L GND V CC SEM R R/W L CE R SEM L UB R CE L LB R UB L NC 6 LB A L 11R NC A 5 10R A A 11L 9R A A 10L 8R A A 7R 9L A 8L