CY7C024AV/025AV/026AV
3.3 V 4 K / 8 K / 16 K 16 Dual-Port
Static RAM
3.3 V 4 K / 8 K / 16 K 16 Dual-Port Static RAM
INT flag for port-to-port communication
Features
Separate upper byte and lower byte control
True dual-ported memory cells which enable simultaneous
access of the same memory location
Pin select for Master or Slave (M/S)
4, 8 or 16 K 16 organization
Commercial and industrial temperature ranges
(CY7C024AV/025AV/026AV)
Available in 100-pin Pb-free TQFP and 100-pin TQFP
0.35 micron CMOS for optimum speed and power
Functional Description
High speed access: 20 ns and 25 ns
The CY7C024AV/025AV/026AV consist of an array of 4 K, 8 K, and
Low operating power
16 K words of 16 bits each of dual-port RAM cells, IO and address
Active: I = 115 mA (typical)
CC
lines, and control signals (CE, OE, R/W). These control pins permit
Standby: I = 10 A (typical)
SB3
independent access for reads or writes to any location in memory.
Fully asynchronous operation To handle simultaneous writes and reads to the same location, a
BUSY pin is provided on each port. Two Interrupt (INT) pins can be
Automatic power down
used for port to port communication. Two Semaphore (SEM) control
pins are used for allocating shared resources. With the M/S pin, the
Expandable data bus to 32 bits or more using Master and Slave
devices can function as a master (BUSY pins are outputs) or as a
chip select when using more than one device
slave (BUSY pins are inputs). They also have an automatic power
On chip arbitration logic
down feature controlled by CE. Each port has its own output enable
control (OE), which enables data to be read from the device.
Semaphores included to permit software handshaking
between ports For a complete list of related resources, click here.
Selection Guide
CY7C024AV/025AV/026AV CY7C024AV/025AV/026AV
Parameter Unit
-20 -25
Maximum Access Time 20 25 ns
Typical Operating Current 120 115 mA
Typical Standby Current for I 35 30 mA
SB1
(Both ports TTL Level)
Typical Standby Current for I 10 10 A
SB3
(Both ports CMOS Level)
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-06052 Rev. *R Revised December 11, 2014CY7C024AV/025AV/026AV
Logic Block Diagram
R/W R/W
L R
UB UB
L R
CE CE
L R
LB LB
L R
OE OE
L R
[1]
8 8
[1]
IO IO IO IO
8L 15L 8L 15R
8 8 [2]
IO IO
[2]
IO IO IO IO
0L 7L 0L 7R
Control Control
12/13/14 12/13/14
[3]
[3] Address Address
True Dual-Ported
A A A A
0L 11/1213L 0R 11/12/13R
RAM Array
Decode Decode
[3]
[3]
12/13/14 12/13/14
A A A A
0L 11/12/13L 0R 11/12/13R
CE CE
Interrupt
L R
OE OE
Semaphore
L R
R/W Arbitration R/W
L R
SEM SEM
L R
[4]
[4]
BUSY BUSY
L R
INT INT
L R
UB UB
L R
LB M/S LB
L R
Notes
1. IO IO for 16 devices
8 15
2. IO IO for 16 devices
0 7
3. A A for 4K devices; A A for 8K devices; A A for 16K devices.
0 11 0 12 0 13
is an output in master mode and an input in slave mode.
4. BUSY
Document Number: 38-06052 Rev. *R Page 2 of 24