CY7C026A16 K 16 Dual-Port Static RAM CY7C026A 16 K 16 Dual-Port Static RAM 16 K 16 Dual-Port Static RAM Features Functional Description True dual-ported memory cells that allow simultaneous access The CY7C026A is a low power CMOS 16 K 16 dual-port static of the same memory location RAM. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same 16 K 16 organization (CY7C026A) piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in 0.35 micron CMOS for optimum speed and power memory. The device can be utilized as standalone 16-bit High speed access: 15, and 20 ns dual-port static RAM or multiple devices can be combined to function as a 32-bit or wider master/slave dual-port static RAM. Low operating power An M/S pin is provided for implementing 32-bit or wider memory Active: I = 180 mA (typical) applications without the need for separate master and slave CC devices or additional discrete logic. Application areas include Standby: I = 0.05 mA (typical) SB3 interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Fully asynchronous operation Each port has independent control pins: Chip Enable (CE), Read Automatic power-down or Write Enable (R/W), and Output Enable (OE). Two flags are Expandable data bus to 32 bits or more using Master/Slave provided on each port (BUSY and INT). BUSY signals that the chip select when using more than one device port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits On-chip arbitration logic communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one Semaphores included to permit software handshaking port to the other to indicate that a shared resource is in use. The between ports semaphore logic is comprised of eight shared latches. Only one INT flags for port-to-port communication side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An Separate upper-byte and lower-byte control automatic power down feature is controlled independently on Pin select for Master or Slave each port by the chip enable pin. The CY7C026A is available in 100-pin thin quad plastic flatpack Commercial and Industrial temperature ranges (TQFP) packages. Available in 100-pin thin quad plastic flatpack (TQFP) For a complete list of related documentation, click here. Pb-free packages available Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06046 Rev. *J Revised November 18, 2015CY7C026A Logic Block Diagram R/W R/W L R UB UB L R CE CE L R LB LB L R OE OE L R 8 8 I/O I/O I/O I/O 8L 15L 8L 15R 8 8 I/O I/O I/O I/O I/O I/O 0L 7L 0L 7R Control Control 14 14 Address True Dual-Ported Address A A A A 0L 13L 0R 13R RAM Array Decode Decode 14 14 A A A A 0L 13L 0R 13R CE CE Interrupt L R OE OE Semaphore L R R/W Arbitration R/W L R SEM SEM L R 1 1 BUSY BUSY L R INT INT L R UB UB L R LB M/S LB L R Note 1. BUSY is an output in master mode and an input in slave mode. Document Number: 38-06046 Rev. *J Page 2 of 24