CY7C027V/027AV/028V/028AV CY7C037AV/038V 3.3 V 32 K / 64 K 16 / 18 Dual-Port Static RAM 3.3 V 32 K / 64 K 16 / 18 Dual-Port Static RAM Automatic power-down Features Expandable data bus to 32/36 bits or more using Master/Slave True dual-ported memory cells which allow simultaneous chip select when using more than one device access of the same memory location On-chip arbitration logic 1 32 K 16 organization (CY7C027V/027AV ) Semaphores included to permit software handshaking 1 64 K 16 organization (CY7C028V/028AV ) between ports 32 K 18 organization (CY7C037AV) INT flag for port-to-port communication 64 K 18 organization (CY7C038V) Separate upper-byte and lower-byte control 0.35 micron Complementary metal oxide semiconductor Dual chip enables (CMOS) for optimum speed and power Pin select for Master or Slave High speed access: 15, 20, and 25 ns Commercial and Industrial temperature ranges Low operating power 100-pin Pb-free Thin quad plastic flatpack (TQFP) and 100-pin Active: I = 115 mA (typical) CC TQFP For a complete list of related documentation, click here. Standby: I = 10 A (typical) SB3 Fully asynchronous operation Logic Block Diagram R/W R/W L R UB UB L R CE CE 0L 0R CE CE 1L 1R CE CE L R LB LB L R OE OE L R 8/9 8/9 2 2 I/O I/O I/O I/O 8/9L 15/17L 8/9L 15/17R 8/9 8/9 3 I/O I/O 3 I/O I/O I/O I/O 0L 7/8L 0L 7/8R Control Control 15/16 15/16 4 Address True Dual-Ported Address 4 A A A A 0L 14/15L 0R 14/15R RAM Array Decode Decode 15/16 15/16 4 4 A A A A 0L 14/15L 0R 14/15R CE Interrupt CE L R OE Semaphore OE L R Arbitration R/W R/W L R SEM SEM L R 5 5 BUSY BUSY L R INT INT L R UB UB L R LB M/S LB L R Notes 1. CY7C027V, and CY7C027AV are functionally identical. CY7C028V and CY7C028AV are functionally identical. 2. I/O I/O for x16 devices I/O I/O for x18 devices. 8 15 9 17 3. I/O I/O for x16 devices I/O I/O for x18 devices. 0 7 0 8 4. A A for 32K A A for 64K devices. 0 14 0 15 5. BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06078 Rev. *I Revised November 20, 2014 CY7C027V/027AV/028V/028AV CY7C037AV/038V Contents Pin Configurations ...........................................................3 Non-Contending Read/Write .......................................... 17 Selection Guide ................................................................5 Interrupt Operation Example ......................................... 17 Pin Definitions ..................................................................5 Semaphore Operation Example .................................... 18 Architecture ......................................................................5 Ordering Information ...................................................... 19 Functional Description .....................................................5 32 K 16 3.3 V Asynchronous Dual-Port SRAM ...... 19 Write Operation ...........................................................5 64 K 16 3.3 V Asynchronous Dual-Port SRAM ...... 19 Read Operation ...........................................................6 32 K 18 3.3 V Asynchronous Dual-Port SRAM ...... 19 Interrupts .....................................................................6 64 K 18 3.3 V Asynchronous Dual-Port SRAM ...... 19 Busy ............................................................................6 Ordering Code Definitions ......................................... 20 Master/Slave ...............................................................6 Package Diagram ............................................................ 21 Semaphore Operation .................................................6 Acronyms ........................................................................22 Maximum Ratings .............................................................7 Document Conventions ................................................. 22 Operating Range ...............................................................7 Units of Measure ....................................................... 22 Electrical Characteristics .................................................7 Document History Page ................................................. 23 Capacitance ......................................................................7 Sales, Solutions, and Legal Information ...................... 24 AC Test Loads and Waveforms .......................................8 Worldwide Sales and Design Support ....................... 24 Data Retention Mode ........................................................8 Products ....................................................................24 Timing ................................................................................8 PSoC Solutions ...................................................... 24 Switching Characteristics ................................................9 Cypress Developer Community ................................. 24 Switching Waveforms ....................................................11 Technical Support ..................................................... 24 Document Number: 38-06078 Rev. *I Page 2 of 24