CY7C02732K/64K 16 Dual-Port Static RAM CY7C027 CY7C028 32K/64K 16 Dual-Port Static RAM 32K/64K 16 Dual-Port Static RAM Features Functional Description True dual-ported memory cells which allow simultaneous The CY7C027 and CY7C028 are low power CMOS 32K, access of the same memory location 64K 16 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple 32K 16 organization (CY7C027) processors access the same piece of data. Two ports are 64K 16 organization (CY7C028) provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be 0.35 micron CMOS for optimum speed and power used as standalone 16-bit dual-port static RAMs or multiple devices can be combined to function as a 32-bit or wider High speed access: 15 and 20 ns master/slave dual-port static RAM. An M/S pin is provided for Low operating power implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional Active: I = 180 mA (typical) CC discrete logic. Application areas include interprocessor and Standby: I = 0.05 mA (typical) multiprocessor designs, communications status buffering, and SB3 dual-port video/graphics memory. Fully asynchronous operation Each port has independent control pins: dual chip enables (CE 0 Automatic power down and CE ), read or write enable (R/W), and output enable (OE). 1 Two flags are provided on each port (BUSY and INT). BUSY Expandable data bus to 32 bits or more using Master/Slave signals that the port is trying to access the same location chip select when using more than one device currently being accessed by the other port. The interrupt flag On-chip arbitration logic (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, Semaphores included to permit software handshaking or token, from one port to the other to indicate that a shared between ports resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) INT flags for port-to-port communication at any time. Control of a semaphore indicates that a shared Separate upper-byte and lower-byte control resource is in use. An automatic power down feature is controlled independently on each port by the chip enable pins. Dual chip enables The CY7C027 and CY7C028 are available in 100-pin Thin Quad Pin select for Master or Slave Flat pack (TQFP) packages. Commercial and industrial temperature ranges For a complete list of related documentation, click here. Available in 100-pin TQFP Pb-free packages available Selection Guide CY7C027/CY7C028 CY7C027/CY7C028 Parameter Unit -15 -20 Maximum Access Time 15 20 ns Typical Operating Current 190 180 mA Typical Standby Current for I (Both ports TTL level) 50 45 mA SB1 Typical Standby Current for I (Both ports CMOS level) 0.05 0.05 mA SB3 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06042 Rev. *M Revised August 1, 2017CY7C027 CY7C028 Logic Block Diagram R/W R/W L R UB UB L R CE CE 0L 0R CE CE 1L 1R CE CE L R LB LB L R OE OE L R 8 8 1 1 I/O I/O I/O I/O 8L 15L 8L 15R 8 8 I/O I/O 2 2 I/O I/O I/O I/O 0L 7L 0L 7R Control Control 15/16 15/16 Address Address 3 True Dual-Ported 3 A A A A 0L 14/15L 0R 14/15R RAM Array Decode Decode 15/16 15/16 3 3 A A A A 0L 14/15L 0R 14/15R CE CE Interrupt L R OE OE Semaphore L R R/W Arbitration R/W L R SEM SEM L R 4 4 BUSY BUSY L R INT INT L R UB UB L R LB M/S LB L R Notes 1. I/O I/O for 16 devices 8 15 2. I/O I/O for 16 devices 0 7 3. A A for 32K A A for 64K devices. 0 14 0 15 4. BUSY is an output in master mode and an input in slave mode. Document Number: 38-06042 Rev. *M Page 2 of 24