CY7C027V/027AV/028V/028AV CY7C037AV/038V 3.3 V, 32K/64K 16/18 Dual-Port Static RAM 3.3 V, 32K/64K 16/18 Dual-Port Static RAM Features Functional Description True dual-ported memory cells which allow simultaneous The CY7C027V/027AV/028V/028AV and CY7037AV/038V are access of the same memory location low power CMOS 32K, 64K 16/18 dual-port static RAMs. 1 Various arbitration schemes are included on the devices to 32K 16 organization (CY7C027V/027AV ) handle situations when multiple processors access the same 1 64K 16 organization (CY7C028V/028AV ) piece of data. Two ports are provided, permitting independent, 32K 18 organization (CY7C037AV) asynchronous access for reads and writes to any location in memory. The devices can be utilized as stand-alone 16/18-bit 64K 18 organization (CY7C038V) dual-port static RAMs or multiple devices can be combined to 0.35 micron Complementary metal oxide semiconductor function as a 32/36-bit or wider master/slave dual-port static (CMOS) for optimum speed and power RAM. An M/S pin is provided for implementing 32/36-bit or wider High speed access: 15, 20, and 25 ns memory applications without the need for separate master and slave devices or additional discrete logic. Application areas Low operating power include interprocessor/multiprocessor designs, communications Active: I = 115 mA (typical) CC status buffering, and dual-port video/graphics memory. Standby: I = 10 A (typical) SB3 Each port has independent control pins: Chip Enable (CE), Read Fully asynchronous operation or Write Enable (R/W), and Output Enable (OE). Two flags are Automatic power-down provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other Expandable data bus to 32/36 bits or more using Master/Slave port. The interrupt flag (INT) permits communication between ports or chip select when using more than one device systems by means of a mail box. The semaphores are used to pass a On-chip arbitration logic flag, or token, from one port to the other to indicate that a shared Semaphores included to permit software handshaking resource is in use. The semaphore logic is comprised of eight shared between ports latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An INT flag for port-to-port communication automatic power down feature is controlled independently on each port Separate upper-byte and lower-byte control by a chip select (CE) pin. Dual chip enables The CY7C027V/027AV/028V/028AV and CY7037AV/038V are Pin select for Master or Slave available in 100-pin Thin Quad Plastic Flatpacks (TQFP). Commercial and Industrial temperature ranges For a complete list of related documentation, click here. 100-pin Pb-free Thin quad plastic flatpack (TQFP) and 100-pin TQFP Selection Guide Parameter -15 -20 -25 Unit Maximum access time 15 20 25 ns Typical operating current 125 120 115 mA Typical standby current for I (Both ports TTL level) 35 35 30 mA SB1 Typical standby current for I (Both ports CMOS level) 10 10 10 A SB3 Note 1. CY7C027V, and CY7C027AV are functionally identical. CY7C028V and CY7C028AV are functionally identical. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06078 Rev. *J Revised January 24, 2018 CY7C027V/027AV/028V/028AV CY7C037AV/038V Logic Block Diagram R/W R/W L R UB UB L R CE CE 0L 0R CE CE 1L 1R CE CE L R LB LB L R OE OE L R 8/9 8/9 2 2 I/O I/O I/O I/O 8/9L 15/17L 8/9L 15/17R 8/9 8/9 3 3 I/O I/O I/O I/O I/O I/O 0L 7/8L 0L 7/8R Control Control 15/16 15/16 4 Address Address 4 True Dual-Ported A A A A 0L 14/15L 0R 14/15R RAM Array Decode Decode 15/16 15/16 4 4 A A A A 0L 14/15L 0R 14/15R CE CE Interrupt L R OE Semaphore OE L R Arbitration R/W R/W L R SEM SEM L R 5 5 BUSY BUSY L R INT INT L R UB UB L R LB M/S LB L R Notes 2. I/O I/O for x16 devices I/O I/O for x18 devices. 8 15 9 17 3. I/O I/O for x16 devices I/O I/O for x18 devices. 0 7 0 8 4. A A for 32K A A for 64K devices. 0 14 0 15 5. BUSY is an output in master mode and an input in slave mode. Document Number: 38-06078 Rev. *J Page 2 of 26