CY7C056V CY7C057V CY7C037V CY7C038V3.3 V 16K/32K 36 FLEx36 Asynchronous Dual-Port Static RAM CY7C056V CY7C057V 3.3 V 16K/32K 36 FLEx36 Asynchronous Dual-Port Static RAM 3.3 V 16K/32K 36 FLEx36 Asynchronous Dual-Port Static RAM Pb-free packages available Features Compact packages: True dual-ported memory cells that allow simultaneous access 144-pin TQFP (20 20 1.4 mm) of the same memory location 172-ball BGA (1.0-mm pitch) (15 15 0.51 mm) 16K 36 organization (CY7C056V) Functional Description 32K 36 organization (CY7C057V) The CY7C056V and CY7C057V are low-power CMOS 16K and 0.25-micron Complimentary metal oxide semiconductor 32K 36 dual-port static RAMs. Various arbitration schemes are (CMOS) for optimum speed/power included on the devices to handle situations when multiple High-speed access: 12/15 ns processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for Low operating power reads and writes to any location in memory. The devices can be Active: I = 250 mA (typical) CC utilized as standalone 36-bit dual-port static RAMs or multiple Standby: I = 10 A (typical) SB3 devices can be combined in order to function as a 72-bit or wider master/slave dual-port static RAM. An M/S pin is provided for Fully asynchronous operation implementing 72-bit or wider memory applications without the Automatic power-down need for separate master and slave devices or additional discrete logic. Application areas include Expandable data bus to 72 bits or more using Master/Slave interprocessor/multiprocessor designs, communications status Chip Select when using more than one device buffering, and dual-port video/graphics memory. On-chip arbitration logic 1 Each port has independent control pins: Chip Enable (CE) , Read or Write Enable (R/W), and Output Enable (OE). Two flags Semaphores included to permit software handshaking are provided on each port (BUSY and INT). BUSY signals that between ports the port is trying to access the same location currently being INT flag for port-to-port communication accessed by the other port. TheInterrupt Flag (INT) permits communication between ports or systems by means of a Byte select on left port mailbox. The semaphores are used to pass a flag, or token, from Bus matching on right port one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only Depth expansion via dual chip enables one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An Pin select for Master or Slave automatic Power-down feature is controlled independently on Commercial and Industrial temperature ranges each port by Chip Select (CE and CE ) pins. 0 1 Available in 144-pin thin quad plastic flatpack (TQFP) or The CY7C056V and CY7C057V are available in 144-pin TQFP 172-ball ball grid array (BGA) and 172-ball BGA packages. For a complete list of related resources, click here. Selection Guide CY7C056V CY7C056V Description CY7C057V CY7C057V Unit -12 -15 Maximum access time 12 15 ns Typical operating current 250 240 mA Typical standby current for I (Both ports TTL level) 55 50 mA SB1 Typical standby current for I (Both ports CMOS level) 10 10 A SB3 Note 1. CE is LOW when CE V and CE V . 0 IL 1 IH Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06055 Rev. *L Revised November 27, 2017CY7C056V CY7C057V Logic Block Diagram R/W R/W L R B B Left Right 0 3 CE CE Port Port 0L 0R CE CE Control Control 1L 1R CE L CE R Logic Logic OE OE L R BA 9 9 WA I/O I/O 0L 8L 9 9 I/O I/O 9/18/36 9L 17L Bus I/O I/O I/O 9 R Match 9 Control Control I/O I/O 18L 26L 9 9 I/O I/O BM 27L 35L SIZE 14/15 14/15 Address Address 2 True Dual-Ported 2 A A A A 0L 13/14L 0R 13/14R RAM Array Decode Decode 14/15 14/15 Interrupt Semaphore Arbitration SEM SEM L R 3 3 BUSY BUSY L R INT INT L R M/S Notes 2. A A for 16K A A for 32K devices. 0 13 0 14 3. BUSY is an output in Master mode and an input in Slave mode. Document Number: 38-06055 Rev. *L Page 2 of 29