CY7C056V CY7C057V CY7C037V CY7C038V3.3 V 16 K / 32 K 36 FLEx36 Asynchronous Dual-Port Static RAM CY7C056V CY7C057V 3.3 V 16 K / 32 K 36 FLEx36 Asynchronous Dual-Port Static RAM 3.3 V 16 K / 32 K 36 FLEx36 Asynchronous Dual-Port Static RAM Compact packages: Features 144-pin TQFP (20 20 1.4 mm) True dual-ported memory cells that allow simultaneous access 172-ball BGA (1.0-mm pitch) (15 15 0.51 mm) of the same memory location Functional Description 16 K 36 organization (CY7C056V) The CY7C056V and CY7C057V are low-power CMOS 16K and 32 K 36 organization (CY7C057V) 32K x 36 dual-port static RAMs. Various arbitration schemes are 0.25-micron Complimentary metal oxide semiconductor included on the devices to handle situations when multiple (CMOS) for optimum speed/power processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for High-speed access: 12/15 ns reads and writes to any location in memory. The devices can be Low operating power utilized as standalone 36-bit dual-port static RAMs or multiple devices can be combined in order to function as a 72-bit or wider Active: I = 250 mA (typical) CC master/slave dual-port static RAM. An M/S pin is provided for Standby: I = 10 A (typical) SB3 implementing 72-bit or wider memory applications without the Fully asynchronous operation need for separate master and slave devices or additional discrete logic. Application areas include Automatic power-down interprocessor/multiprocessor designs, communications status Expandable data bus to 72 bits or more using Master/Slave buffering, and dual-port video/graphics memory. Chip Select when using more than one device 1 Each port has independent control pins: Chip Enable (CE) , Read or Write Enable (R/W), and Output Enable (OE). Two flags On-chip arbitration logic are provided on each port (BUSY and INT). BUSY signals that Semaphores included to permit software handshaking the port is trying to access the same location currently being between ports accessed by the other port. TheInterrupt Flag (INT) permits communication between ports or systems by means of a INT flag for port-to-port communication mailbox. The semaphores are used to pass a flag, or token, from Byte select on left port one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only Bus matching on right port one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An Depth expansion via dual chip enables automatic Power-down feature is controlled independently on Pin select for Master or Slave each port by Chip Select (CE and CE ) pins. 0 1 Commercial and Industrial temperature ranges The CY7C056V and CY7C057V are available in 144-pin Thin quad plastic flatpack (TQFP) and 172-ball ball grid array (BGA) Available in 144-pin Thin quad plastic flatpack (TQFP) or packages. 172-ball ball grid array (BGA) For a complete list of related resources, click here. Pb-free packages available Note 1. CE is LOW when CE V and CE V . 0 IL 1 IH Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06055 Rev. *J Revised November 18, 2015CY7C056V CY7C057V Logic Block Diagram R/W R/W L R B B Left Right 0 3 CE CE Port Port 0L 0R CE CE Control Control 1L 1R CE L CE R Logic Logic OE OE L R BA 9 9 WA I/O I/O 0L 8L 9 9 I/O I/O 9/18/36 9L 17L Bus I/O I/O I/O 9 R Match 9 Control Control I/O I/O 18L 26L 9 9 I/O I/O BM 27L 35L SIZE 14/15 14/15 Address Address 2 True Dual-Ported 2 A A A A 0L 13/14L 0R 13/14R RAM Array Decode Decode 14/15 14/15 Interrupt Semaphore Arbitration SEM SEM L R 3 3 BUSY BUSY L R INT INT L R M/S Notes 2. A A for 16K A A for 32K devices. 0 13 0 14 3. BUSY is an output in Master mode and an input in Slave mode. Document Number: 38-06055 Rev. *J Page 2 of 29