CY7C0831AV
CY7C0832AV
CY7C0833V
FLEx18 3.3 V, 128K/256K/512K 18
Synchronous Dual-Port RAM
FLEx18 3.3 V, 128K/256K/512K 18 Synchronous Dual-Port RAM
Features Functional Description
True dual-ported memory cells that allow simultaneous access The FLEx18 family includes 2-Mbit, 4-Mbit, and 9-Mbit
of the same memory location pipelined, synchronous, true dual port static RAMs that are high
speed, low power 3.3V CMOS. Two ports are provided,
Synchronous pipelined operation
permitting independent, simultaneous access to any location in
memory. The result of writing to the same location by more than
Family of 2-Mbit, 4-Mbit, and 9-Mbit devices
one port at the same time is undefined. Registers on control,
Pipelined output mode allows fast operation
address, and data lines allow for minimal setup and hold time.
0.18 micron CMOS for optimum speed and power During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
High speed clock to data access
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
3.3 V low power
details to follow). The internal Write pulse width is independent
Active as low as 225 mA (typ)
of the duration of the R/W input signal. The internal Write pulse
Standby as low as 55 mA (typ)
is self-timed to allow the shortest possible cycle times.
Mailbox function for message passing
A HIGH on CE or LOW on CE for one clock cycle powers down
0 1
the internal circuitry to reduce the static power consumption. One
Global master reset
cycle with chip enables asserted is required to reactivate the
Separate byte enables on both ports
outputs.
Commercial and Industrial temperature ranges Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
IEEE 1149.1 compatible JTAG boundary scan
control the counter wrap around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
144-ball FBGA (13 mm 13 mm (1.0 mm pitch))
retransmit functionality, interrupt flags for message passing,
120-pin TQFP (14 mm 14 mm 1.4 mm)
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
Pb-free packages available
The CY7C0833V device in this family has limited features. See
Counter wrap around control
Address Counter and Mask Register Operations on page 8 for
Internal mask register controls counter wrap around
details.
Counter-interrupt flags to indicate wrap around
For a complete list of related documentation, click here.
Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual chip enables on both ports for easy depth expansion
Product Selection Guide
2-Mbit 4-Mbit 9-Mbit
Density
(128K 18) (256K 18) (512K 18)
Part Number CY7C0831AV CY7C0832AV CY7C0833V
Maximum Speed (MHz) 133 167 100
Maximum Access Time - Clock to Data (ns) 4.0 4.0 4.7
Typical Operating Current (mA) 225 225 270
Package 120-pin TQFP 120-pin TQFP 144-ball FBGA
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-06059 Rev. AA Revised August 1, 2017CY7C0831AV
CY7C0832AV
CY7C0833V
[1]
Logic Block Diagram
OE OE
L R
R/W R/W
L R
B0 B0
L R
B1 B1
L R
CE CE
0L 0R
CE CE
1L 1R
I/O I/O
9 9
DQ DQ Control Control DQ DQ
9L 17L 9R 17R
9 9
DQ DQ
DQ DQ
0L 8L
0R 8R
Addr.
Addr.
Read
Read
True Back
Back
Dual-Ported
RAM Array
19 19
A A
A A
0L 18L
0R 18R
Mask Register Mask Register
CNT/MSK
CNT/MSK
R
L
ADS
ADS Counter/ Counter/
L
Address Address
Address Address
CNTEN
CNTEN
L
Register Register
Decode Decode
CNTRST
CNTRST
R
L
Mirror Reg
Mirror Reg
CLK
CLK
L
R
CNTINT
CNTINT R
L
TMS
Reset
Interrupt Interrupt
MRST JTAG TDO
TDI
Logic
INT INT
L R
Logic Logic
TCK
Note
1. CY7C0831AV has 17 address bits, CY7C0832AV has 18 address bits and CY7C0833V has 19 address bits.
Document Number: 38-06059 Rev. AA Page 2 of 33