CY7C09099V-12AXC Infineon

CY7C09099V 3.3 V, 128K 8 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K 8/9 Synchronous Dual-Port Static RAM Fully synchronous interface for easier operation Features Burst counters increment addresses internally True Dual-Ported memory cells which enable simultaneous access of the same memory location Shorten cycle times Flow-through and Pipelined devices Minimize bus noise 128K 8 organizations (CY7C09099V) Supported in Flow-through and Pipelined modes Three Modes Dual Chip Enables for easy depth expansion Flow-through Automatic power down Pipelined Commercial and Industrial temperature ranges Burst Pipelined output mode on both ports enables fast 100-MHz Available in 100-pin TQFP operation Pb-free packages available 0.35-micron CMOS for optimum speed and power 1 For a complete list of related documentation, click here. High-speed clock to data access 7.5 /12 ns (max.) 3.3-V low operating power Active = 115 mA (typical) Standby = 10 A (typical) Note 1. See page 8 and page 9 for Load Conditions. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06043 Rev. *J Revised July 12, 2017CY7C09099V Logic Block Diagram R/W R/W L R OE OE L R CE CE 0L 0R 1 1 CE CE 1L 1R 0 0 0/1 0/1 1 0 0 1 0/1 0/1 FT/Pipe FT/Pipe L R 2 8/9 8/9 2 I/O I/O I/O I/O 0L 7/8L 0R 7/8R I/O I/O Control Control 15/16/17 15/16/17 3 3 A A A A 0 14/15/16L 0 14/15/16R Counter/ Counter/ CLK CLK L R Address True Dual-Ported Address ADS ADS L R Register RAM Array Register CNTEN CNTEN L R Decode Decode CNTRST CNTRST L R Notes 2. I/O I/O for 8 devices, I/O I/O for 9 devices. 0 7 0 8 3. A A for 32K and A A for 128K devices. 0 14 0 16 Document Number: 38-06043 Rev. *J Page 2 of 27