CY7C09169AVTITLE CY7C09159AV 3.3-V 8 K 9 Synchronous Dual Port Static RAM 3.3 V Low operating power Features Active = 135 mA (typical) True dual-ported memory cells which allow simultaneous Standby = 10 A (typical) access of the same memory location Fully synchronous interface for easier operation Flow-through/Pipelined device Burst counters increment addresses internally 8 K 9 organization (CY7C09159AV) Shorten cycle times Three Modes Minimize bus noise Flow-through Supported in Flow-through and Pipelined modes Pipelined Dual chip enables for easy depth expansion Burst Automatic power-down Pipelined output mode on both ports allows fast 67-MHz operation Commercial temperature ranges 0.35-micron complementary metal oxide semiconductor Available in 100-pin thin quad plastic flatpack (TQFP) (CMOS) for optimum speed/power Pb-free packages available High-speed clock to data access 9 ns (max.) For a complete list of related documentation, click here. Logic Block Diagram R/W R/W L R OE OE L R CE CE 0L 1 1 0R CE CE 1L 1R 0 0 0/1 0/1 1 0 0 1 0/1 0/1 FT/Pipe FT/Pipe L R 9 9 I/O I/O I/O I/O 0L 8L 0R 8R I/O I/O Control Control 13 13 A A A A 0 12L 0 12R Counter/ Counter/ CLK CLK L R Address True Dual-Ported Address ADS ADS L R Register RAM Array Register CNTEN CNTEN L R Decode Decode CNTRST CNTRST L R Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06053 Rev. *F Revised November 20, 2014 CY7C09159AV Functional Description The CY7C09159AV is a high-speed synchronous CMOS 8 K 9 banking of multiple chips for depth expansion configurations. In dual-port static RAM. Two ports are provided, permitting the pipelined mode, one cycle is required with CE LOW and CE 0 1 independent, simultaneous access for reads and writes to any HIGH to reactivate the outputs. 1 location in memory. Registers on control, address, and data Counter enable inputs are provided to stall the operation of the lines allow for minimal setup and hold times. In pipelined output address input and utilize the internal address generated by the mode, data is registered for decreased cycle time. Clock to data internal counter for fast interleaved memory applications. A valid t = 9 ns (pipelined). Flow-through mode can also be CD2 ports burst counter is loaded with the ports Address Strobe used to bypass the pipelined output register to eliminate access (ADS). When the ports Count Enable (CNTEN) is asserted, the latency. In flow-through mode data will be available t = 20 ns CD1 address counter will increment on each LOW-to-HIGH transition after the address is clocked into the device. Pipelined output or of that ports clock signal. This will read/write one word from/into flow-through mode is selected via the FT/Pipe pin. each successive address location until CNTEN is deasserted. Each port contains a burst counter on the input address register. The counter can address the entire memory array and will loop The internal write pulse width is independent of the back to the start. Counter Reset (CNTRST) is used to reset the LOW- to-HIGH transition of the clock signal. The internal write burst counter. pulse is self-timed to allow the shortest possible cycle times. All parts are available in 100-pin thin quad plastic flatpack A HIGH on CE or LOW on CE for one clock cycle will power (TQFP) packages. 0 1 down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier Note 1. When simultaneously writing to the same location, final value cannot be guaranteed. Document Number: 38-06053 Rev. *F Page 2 of 19