CY7C09359AV3.3 V 4 K/8 K 18 Synchronous Dual Port Static RAM CY7C09349AV CY7C09359AV 3.3 V 4 K/8 K 18 Synchronous Dual Port Static RAM 3.3 V 4 K/8 K 18 Synchronous Dual Port Static RAM High-speed clock to data access 9 and 12 ns (max) Features 3.3 V low operating power True dual ported memory cells which allow simultaneous Active = 135 mA (typical) access of the same memory location Standby = 10 A (typical) Two flow-through/pipelined devices Fully synchronous interface for easier operation 4 K 18 organization (CY7C09349AV) 8 K 18 organization (CY7C09359AV) Burst counters increment addresses internally Shorten cycle times Three modes Minimize bus noise Flow-through Supported in flow-through and pipelined modes Pipelined Burst Dual chip enables for easy depth expansion Pipelined output mode on both ports allows fast 67-MHz Upper and lower byte controls for bus matching operation Automatic power-down 0.35-micron complementary metal oxide semiconductor Available in 100-pin thin quad flat pack (TQFP) (CMOS) for optimum speed/power For a complete list of related documentation, click here. Logic Block Diagram R/W R/W L R UB UB L R CE CE 0L 1 1 0R CE CE 1L 1R 0 0 0/1 0/1 LB LB L R OE OE L R 1b 0b 1a 0a 0a 1a 0b 1b 0/1ba a b 0/1 FT/Pipe FT/Pipe L R 9 9 I/O I/O I/O I/O 9L 17L 9R 17R I/O I/O Control Control 9 9 I/O I/O I/O I/O 0L 8L 0R 8R 12/13 12/13 1 1 A A A A 0L 11/12L 0R 11/12R Counter/ Counter/ CLK CLK L R Address True Dual Ported Address ADS ADS L R Register RAM Array Register CNTEN CNTEN L Decode Decode R CNTRST CNTRST L R Note A for 4 K A A for 8 K devices. 1. A 0 11 0 12 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-63888 Rev. *C Revised November 26, 2014CY7C09349AV CY7C09359AV A HIGH on CE or LOW on CE for one clock cycle will power Functional Description 0 1 down the internal circuitry to reduce the static power consumption. The use of multiple chip enables allows easier The CY7C09349AV and CY7C09359AV are high-speed 3.3 V banking of multiple chips for depth expansion configurations. In synchronous CMOS 4 K and 8 K 18 dual-port static RAMs. Two the pipelined mode, one cycle is required with CE LOW and CE ports are provided, permitting independent, simultaneous 0 1 2 HIGH to reactivate the outputs. access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal Counter enable inputs are provided to stall the operation of the set-up and hold times. In pipelined output mode, data is address input and utilize the internal address generated by the registered for decreased cycle time. Clock to data valid internal counter for fast interleaved memory applications. A t = 9 ns (pipelined). Flow-through mode can also be used to CD2 ports burst counter is loaded with the ports address strobe bypass the pipelined output register to eliminate access latency. (ADS). When the ports count enable (CNTEN) is asserted, the In flow-through mode data will be available t = 20 ns after the CD1 address counter will increment on each LOW-to-HIGH transition address is clocked into the device. Pipelined output or of that ports clock signal. This will read/write one word from/into flow-through mode is selected via the FT/Pipe pin. each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop Each port contains a burst counter on the input address register. back to the start. Counter reset (CNTRST) is used to reset the The internal write pulse width is independent of the burst counter. LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. All parts are available in 100-pin thin quad plastic flatpack (TQFP) packages. Note 2. When simultaneously writing to the same location, final value cannot be guaranteed. Document Number: 001-63888 Rev. *C Page 2 of 20