CY7C09389V-12AC Infineon

CY7C09269V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM 3.3V low operating power: Features Active = 115 mA (typical) True dual-ported memory cells that allow simultaneous access Standby = 10 A (typical) of the same memory location Fully synchronous interface for easier operation Six flow through/pipelined devices: Burst counters increment addresses internally: 16K x 16/18 organization (CY7C09269V/369V) Shorten cycle times 32K x 16/18 organization (CY7C09279V/379V) Minimize bus noise 64K x 16/18 organization (CY7C09289V/389V) Supported in flow through and pipelined modes Three modes: Dual chip enables easy depth expansion Flow through Pipelined Upper and lower byte controls for bus matching Burst Automatic power down Pipelined output mode on both ports allows fast 100 MHz Commercial and industrial temperature ranges operation Pb-Free 100-pin TQFP package available 0.35 micron CMOS for optimum speed and power [1, 2] [2] High speed clock to data access: 6.5 , 7.5 , 9, 12 ns (max) Logic Block Diagram R/W R/W L R UB UB L R CE CE 0L 1 1 0R CE CE 1L 1R 0 0 0/1 0/1 LB LB L R OE OE L R 1b 0b 1a 0a 0a 1a 0b 1b 0/1ba a b 0/1 FT/Pipe FT/Pipe L R 8/9 8/9 [3] [3] I/O I/O I/O I/O 8/9L 15/17L 8/9R 15/17R I/O I/O Control Control 8/9 8/9 [4] [4] I/O I/O I/O I/O 0L 7/8L 0R 7/8R 14/15/16 14/15/16 [5] [5] A A A A 0L 13/14/15L 0R 13/14/15R Counter/ Counter/ CLK CLK L R Address True Dual-Ported Address ADS ADS L R Register RAM Array Register CNTEN CNTEN Decode Decode L R CNTRST CNTRST L R Notes 1. Call for availability. 2. See page 6 for Load Conditions. 3. I/O I/O for x16 devices; I/O I/O for x18 devices. 8 15 9 17 4. I/O I/O for x16 devices. I/O I/O for x18 devices. 0 7 0 8 5. A A for 16K; A A for 32K; A A for 64K devices. 0 13 0 14 0 15 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document #: 38-06056 Rev. *C Revised March 25, 2009 [+] Feedback [+] Feedback CY7C09269V/79V/89V CY7C09369V/79V/89V Pinouts Figure 1. 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A9R A10L 2 74 A10R A11L 3 73 A11R A12L 4 72 A12R A13L 5 71 A13R [6] A14L 6 70 A14R [6] [7] [7] A15L 7 69 A15R NC 8 68 NC NC 9 67 NC LBL 10 66 LBR UBL 11 65 UBR CY7C09289V (64K x 16) CE0L 12 64 CE0R CE1L 13 63 CE1R CY7C09279V (32K x 16) CNTRSTL 14 62 CNTRSTR VCC 15 61 GND CY7C09269V (16K x 16) R/WL 16 60 R/WR OEL 17 59 OER FT/PIPEL 18 58 FT/PIPER [8] GND 19 57 GND [8] I/O15L 20 56 I/O15R I/O14L 21 55 I/O14R I/O13L 22 54 I/O13R I/O12L 23 53 I/O12R I/O11L 24 52 I/O11R I/O10L 25 51 I/O10R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes 6. This pin is NC for CY7C09269V. 7. This pin is NC for CY7C09269V and CY7C09279V. 8. For CY7C09269V and CY7C09279V, pin #18 connected to V is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin compatible CC to an IDT 5V x16 flow through device. Document #: 38-06056 Rev. *C Page 2 of 19 [+] Feedback [+] Feedback I/O9L A8L I/O8L A7L VCC A6L I/O7L A5L I/O6L A4L I/O5L A3L I/O4L A2L I/O3L A1L I/O2L A0L GND CNTENL I/O1L CLKL I/O0L ADSL GND GND I/O0R ADSR I/01R CLKR I/O2R CNTENR I/O3R A0R I/O4R A1R I/O5R A2R I/O6R A3R VCC A4R I/O7R A5R I/O8R A6R I/O9R A7R NC A8R