CY7C109D CY7C1009D 1-Mbit (128 K 8) Static RAM 1-Mbit (128 K 8) Static RAM (OE), and tri-state drivers.The eight input and output pins (I/O Features 0 through I/O ) are placed in a high-impedance state when: 7 Pin- and function-compatible with CY7C109B/CY7C1009B Deselected (CE HIGH or CE LOW), 1 2 High speed Outputs are disabled (OE HIGH), t = 10 ns AA When the write operation is active (CE LOW, CE HIGH, and Low active power 1 2 WE LOW) I = 80 mA at 10 ns CC Write to the device by taking Chip Enable One (CE ) and Write 1 Low CMOS standby power Enable (WE) inputs LOW and Chip Enable Two (CE ) input 2 I = 3 mA SB2 HIGH. Data on the eight I/O pins (I/O through I/O ) is then 0 7 2.0 V Data Retention written into the location specified on the address pins (A through 0 Automatic power-down when deselected A ). 16 TTL-compatible inputs and outputs Read from the device by taking Chip Enable One (CE ) and 1 Output Enable (OE) LOW while forcing Write Enable (WE) and Easy memory expansion with CE , CE and OE options 1 2 Chip Enable Two (CE ) HIGH. Under these conditions, the 2 CY7C109D available in Pb-free 32-pin 400-Mil wide Molded contents of the memory location specified by the address pins SOJ and 32-pin TSOP I packages. CY7C1009D available in appears on the I/O pins. Pb-free 32-pin 300-Mil wide Molded SOJ package The CY7C109D/CY7C1009D device is suitable for interfacing Functional Description with processors that have TTL I/P levels. It is not suitable for 1 processors that require CMOS I/P levels. Please see Electrical The CY7C109D/CY7C1009D is a high-performance CMOS Characteristics on page 4 for more details and suggested static RAM organized as 131,072 words by 8 bits. Easy memory alternatives. expansion is provided by an active LOW Chip Enable (CE ), an 1 active HIGH Chip Enable (CE ), an active LOW Output Enable For a complete list of related documentation, click here. 2 Logic Block Diagram INPUT BUFFER IO 0 IO 1 A 0 A IO 1 2 A 2 A 128K x 8 IO 3 3 A 4 A ARRAY IO 5 4 A 6 A IO 7 5 A 8 IO 6 POWER IO 7 CE COLUMN DECODER 1 DOWN CE 2 WE OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05468 Rev. *J Revised January 16, 2015 ROW DECODER A 9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 SENSE AMPSCY7C109D CY7C1009D Contents Pin Configurations ...........................................................3 Ordering Information ...................................................... 11 Selection Guide ................................................................3 Ordering Code Definitions ......................................... 11 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 12 Operating Range ...............................................................4 Acronyms ........................................................................14 Electrical Characteristics .................................................4 Document Conventions ................................................. 14 Capacitance ......................................................................5 Units of Measure ....................................................... 14 Thermal Resistance ..........................................................5 Document History Page ................................................. 15 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 16 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 16 Data Retention Waveform ................................................6 Products ....................................................................16 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 16 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 16 Truth Table ......................................................................11 Technical Support ..................................................... 16 Note 1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com. Document Number: 38-05468 Rev. *J Page 2 of 16