CY7C1010DV33-10ZSXIT Infineon

CY7C1010DV33 2-Mbit (256K x 8) Static RAM Features Functional Description Pin and function compatible with CY7C1010CV33 The CY7C1010DV33 is a high performance CMOS Static RAM organized as 256K words by 8 bits. Easy memory expansion is High speed provided by an active LOW Chip Enable (CE), an active LOW t = 10 ns Output Enable (OE), and three-state drivers. Writing to the AA device is accomplished by taking Chip Enable (CE) and Write Low active power Enable (WE) inputs LOW. Data on the eight I/O pins (I/O 0 I = 90 mA at 10 ns CC through I/O ) is then written into the location specified on the 7 Low CMOS standby power address pins (A through A ). 0 17 I = 10 mA Reading from the device is accomplished by taking Chip Enable SB2 (CE) and Output Enable (OE) LOW while forcing Write Enable 2.0V data retention (WE) HIGH. Under these conditions, the contents of the memory Automatic power down when deselected location specified by the address pins will appear on the I/O pins. The eight input and output pins (I/O through I/O ) are placed in TTL-compatible inputs and outputs 0 7 a high impedance state when the device is deselected (CE Easy memory expansion with CE and OE features HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). Available in Pb-Free 36-pin SOJ and 44-pin TSOP II packages The CY7C1010DV33 is available in 36-pin SOJ and 44-pin TSOP II packages with center power and ground (revolutionary) pinout. Refer to the Cypress application note AN1064, SRAM System Guidelines for best practice recommendations. Logic Block Diagram IO INPUT BUFFER 0 A 0 IO A 1 1 A 2 IO A 2 3 A 4 256K x 8 IO A 3 5 A 6 IO ARRAY A 4 7 A 8 IO A 5 9 A 10 IO 6 CE IO POWER 7 COLUMN DECODER WE DOWN OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-00062 Rev. *B Revised November 6, 2008 + Feedback ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 SENSE AMPSCY7C1010DV33 Selection Guide Description 10 Unit Maximum Access Time 10 ns Maximum Operating Current 90 mA Maximum CMOS Standby Current 10 mA Pin Configuration 1 1 Figure 1. 36-Pin SOJ Figure 2. 44-Pin TSOP II NC 1 44 NC 2 NC NC 43 A 1 36 NC 4 A 3 NC 42 4 A A 2 35 5 3 A A 4 41 5 3 A A 3 34 2 6 A 5 A 40 2 6 A A 4 33 1 7 A A 6 39 1 7 A 5 32 A 0 8 A A 7 38 0 8 6 31 CE OE CE 8 37 OE IO 30 IO 7 0 7 IO 9 IO 36 0 7 IO 8 29 IO 1 6 IO IO 10 1 35 6 V 9 28 CC GND V V 11 34 SS CC V GND 10 27 CC V 12 V SS 33 CC IO 26 IO 2 11 5 IO IO 13 32 2 5 IO IO 3 12 25 4 IO IO 14 3 31 4 A WE 9 13 24 A 15 30 WE 9 A A 17 14 23 10 A A 16 29 17 10 A A 16 15 22 11 A A 17 28 16 11 A A 21 15 16 12 A A 18 27 15 12 A NC 14 20 17 A 19 26 NC 14 A 13 NC 18 19 A 20 25 NC 13 NC 21 24 NC 22 NC 23 NC Note: 1. NC pins are not connected on the die. Document Number: 001-00062 Rev. *B Page 2 of 11 + Feedback